User:He!ko/Books/X86

Architecture & Instructions

 * X86
 * 3DNow!
 * A20 line
 * AES instruction set
 * Adjust flag
 * CLMUL instruction set
 * CPUID
 * Call gate
 * Direction flag
 * Dual-voltage CPU
 * F00f
 * FLAGS register (computing)
 * FMA instruction set
 * Global Descriptor Table
 * High memory
 * Hyper-threading
 * IA-32
 * ICOMP
 * Intel APIC Architecture
 * Intel Turbo Boost
 * Interrupt descriptor table
 * Local Descriptor Table
 * MS-DOS API
 * Maximum mode
 * Microspace PC
 * Minimum mode
 * MultiProcessor Specification
 * PCI hole
 * PSE-36
 * Page Size Extension
 * Pentium FDIV bug
 * Physical Address Extension
 * Privilege level
 * Ralf Brown's Interrupt List
 * Segment descriptor
 * Task State Segment
 * Time Stamp Counter
 * Trap flag
 * Trusted Execution Technology
 * Wintel
 * X86 assembly language
 * X86 calling conventions
 * X86 virtualization
 * X86-64
 * X87
 * Zero flag


 * X86 Instructions
 * X86 instruction listings
 * Intel BCD opcode
 * Advanced Vector Extensions
 * Extended MMX
 * FCMOV
 * HLT
 * IF (x86 flag)
 * INT (x86 instruction)
 * JMP (x86 instruction)
 * LOADALL
 * Load Task Register
 * MMX (instruction set)
 * MOV (x86 instruction)
 * MOVAPD
 * MOVDDUP
 * MOVHPD
 * NOP
 * SSE2
 * SSE3
 * SSE4
 * SSE5
 * SSSE3
 * Streaming SIMD Extensions
 * TEST (x86 instruction)
 * VEX prefix
 * X86 debug register
 * XOP instruction set