User:Hermanbudde

Xetal

Xetal is the name for a family of massively parallel processors developed within Philips Research and NXP research.

Background

The idea for the Xetal processor was born around 1999 within Philips Research. Possibilities were investigated for combining a CMOS image sensor with a powerful image processing logic. Since CMOS image sensors (contrary to CCD sensors) can be produced using the same manufacturing process as integrated circuit (ic) both the image sensor as well as image processing logic could be combined in a single ic. With both image sensor and image processing logic on the same chip it is essentially possible to parallelize image processing up to the level where each pixel has its dedicated image processing logic. In such a design the image sensor would be in the top layers of the integrated circuit. The image processing would be done in the lower layers, image data would be transferred from one layer to the other, instead of through external pins or wires. Additionally there is inherent parallelism in image processing algorithms. Many algorithms do the same processing on every pixel. Image processing is therefore a suitable domain for a massively parallel approach. Although massive parallelism is not a new idea (ILLIAC IV, Goodyear MPP) the Xetal1 was one of the first to apply this approach to image processing.

Initial design

The first design combined a QVGA image sensor with line based A/D conversion. So the analogue pixel values of the sensor were converted line by line (instead of pixel by pixel). For every line there were 320 A/D converters. Each A/D Converter is connected to a dedicated processing element (PE) to do image processing. This parallel design meant that a complete line of 320 pixels could essentially be processed in a single clock cycle. This parallelism was also applied to the memory architecture, each processing element could access a pixel from a so called Line Memory. Simulations of this design showed that the digital (PE) part of the chip caused noise on the A/D converters. On top of that CMOS sensors at the time were produced using a 350nm process using 3 metal layers. Few layers are used to limit height variations in the sensor surface which would cause artifacts. For discrete logic the 180nm process was more common. Also, more layers are used. Development of the CMOS sensor and the image processor therefore continued independently.

Xetal1

For the image processor this resulted in the Xetal-1, first silicon was produced in 2001. The Xetal1 was produced using a 180nm process. It was designed to run at 18Mhz with 320 PE's and 16 Line memories. Since each of the PEs can perform one operation per clock-cycle the raw performance at this clock speed is 5.7 Gops. Meaning that combined with a CMOS image sensor at QVGA resolution running at 15 frames per second the Xetal1 could essentially perform 5000 operations per pixel. During testing it turned out the Xetal1 could even be clocked to 38Mhz, more than double the original specification, resulting in a raw performance of over 12Gops. Moreover, the Xetal1 achieved this performance at very low power consumption (1-2Watt). It was soon discovered that with these levels of performance it was possible to do far more than image processing. Demonstrators were created that showed the Xetal1 was capable of running computer vision algorithms such as object recognition and tracking (Pinball, Drumming, Robocup).