User:Honeydurga/IP, ARM, Xscale and PXA320

Intellectual property
Intellectual property (IP) refers to creations of the mind: inventions, literary and artistic works, and symbols, names, images, and designs used in commerce. IP is divided into two categories:
 * Industrial property, which includes inventions (patents), trademarks, industrial designs, and geographic indications of source; and
 * Copyright: which includes architectural designs.

ARM Holdings
ARM Holdings is the world's leading semiconductor intellectual property (IP) supplier. The ARM business model involves the designing and licensing of IP rather than the manufacturing and selling of actual semiconductor chips. They licence IP to a network of Partners, which includes the world's leading semiconductor and systems companies. These Partners utilize ARM IP designs to create and manufacture system-on-chip designs, paying ARM a license fee for the original IP and a royalty on every chip or wafer produced. In addition to processor IP, ARM Holdings provide a range of tools, physical and systems IP to enable optimized system-on-chip designs. As of 2007, about 98 percent of the more than one billion mobile phones sold each year use at least one ARM processor. As of 2009, ARM processors account for approximately 90% of all embedded 32-bit RISC processors.

The ARM is a 32-bit reduced instruction set computer (RISC) instruction set architecture (ISA) developed by ARM Holdings. ARM processors are developed by ARM and by ARM licensees. Prominent ARM processor families developed by ARM Holdings include the ARM7, ARM9, ARM11 and Cortex. Notable ARM processors developed by licensees include DEC StrongARM, Freescale i.MX, Marvell (formerly Intel) XScale, Nintendo, Nvidia Tegra, ST-Ericsson Nomadik, Qualcomm Snapdragon, the Texas Instruments OMAP product line, the Samsung Hummingbird and the Apple A4.

ARM cores
ARM provides a summary of the numerous vendors who implement ARM cores in their design. KEIL also provides a somewhat newer summary of vendors of ARM based processors. ARM further provides a chart displaying an overview of the ARM processor lineup with performance and functionality versus capabilities for the more recent ARM7, ARM9, ARM11, Cortex-M, Cortex-R and Cortex-A device families.

Architecture
From 1995 onwards, the ARM Architecture Reference Manual has been the primary source of documentation on the ARM processor architecture and instruction set, distinguishing interfaces that all ARM processors are required to support (such as instruction semantics) from implementation details that may vary. The architecture has evolved over time, and starting with the Cortex series of cores, three "profiles" are defined:
 * "Application" profile: Cortex-A series
 * "Real-time" profile: Cortex-R series
 * "Microcontroller" profile: Cortex-M series

Profiles are allowed to subset the architecture. For example the ARMv7-M profile used by the Cortex-M3 core is notable in that it supports only the Thumb-2 instruction set, and the ARMv6-M profile (used by the Cortex-M0) is a subset of the ARMv7-M profile (supporting fewer instructions).

Pipelines and other implementation issues
The ARM7 and earlier implementations have a three stage pipeline; the stages being fetch, decode, and execute. Higher performance designs, such as the ARM9, have deeper pipelines: Cortex-A8 has thirteen stages. Additional implementation changes for higher performance include a faster adder, and more extensive branch prediction logic. The difference between the ARM7DI and ARM7DMI cores, for example, was an improved multiplier (hence the added "M").

Coprocessors
The architecture provides a non-intrusive way of extending the instruction set using "coprocessors" which can be addressed using MCR, MRC, MRRC, MCRR, and similar instructions. The coprocessor space is divided logically into 16 coprocessors with numbers from 0 to 15, coprocessor 15 (cp15) being reserved for some typical control functions like managing the caches and MMU operation (on processors that have one).

In ARM-based machines, peripheral devices are usually attached to the processor by mapping their physical registers into ARM memory space or into the coprocessor space or connecting to another device (a bus) which in turn attaches to the processor. Coprocessor accesses have lower latency so some peripherals (for example XScale interrupt controller) are designed to be accessible in both ways (through memory and through coprocessors). In other cases, chip designers only integrate hardware using the coprocessor mechanism. For example, an image processing engine might be a small ARM7TDMI core combined with a coprocessor that has specialized operations to support a specific set of HDTV transcoding primitives.

Debugging
All modern ARM processors include hardware debugging facilities; without them, software debuggers could not perform basic operations like halting, stepping, and breakpointing of code starting from reset. These facilities are built using JTAG support, though some newer cores optionally support ARM's own two-wire "SWD" protocol. In ARM7TDMI cores, the "D" represented JTAG debug support, and the "I" represented presence of an "EmbeddedICE" debug module. For ARM7 and ARM9 core generations, EmbeddedICE over JTAG was a de-facto debug standard, although it was not architecturally guaranteed.

The ARMv7 architecture defines basic debug facilities at an architectural level. These include breakpoints, watchpoints, and instruction execution in a "Debug Mode"; similar facilities were also available with EmbeddedICE. Both "halt mode" and "monitor" mode debugging are supported. The actual transport mechanism used to access the debug facilities is not architecturally specified, but implementations generally include JTAG support.

There is a separate ARM "CoreSight" debug architecture, which is not architecturally required by ARMv7 processors.

DSP enhancement instructions
To improve the ARM architecture for digital signal processing and multimedia applications, a few new instructions were added to the set. These are signified by an "E" in the name of the ARMv5TE and ARMv5TEJ architectures. E-variants also imply T,D,M and I.

The new instructions are common in digital signal processor architectures. They are variations on signed multiply-accumulate, saturated add and subtract, and count leading zeros.

Thumb
To improve compiled code-density, processors since the ARM7TDMI have featured the Thumb instruction set state. (The "T" in "TDMI" indicates the Thumb feature.) When in this state, the processor executes the Thumb instruction set, a variable-length instruction set providing 32-bit and 16-bit instructions. Most of the Thumb instructions are directly mapped to normal ARM instructions. The space-saving comes from making some of the instruction operands implicit and limiting the number of possibilities compared to the ARM instructions executed in the ARM instruction set state.

In Thumb, the 16-bit opcodes have less functionality. For example, only branches can be conditional, and many opcodes are restricted to accessing only half of all of the CPU's general purpose registers. The shorter opcodes give improved code density overall, even though some operations require extra instructions. In situations where the memory port or bus width is constrained to less than 32 bits, the shorter Thumb opcodes allow increased performance compared with 32-bit ARM code, as less program code may need to be loaded into the processor over the constrained memory bandwidth.

Embedded hardware, such as the Game Boy Advance, typically have a small amount of RAM accessible with a full 32-bit datapath; the majority is accessed via a 16 bit or narrower secondary datapath. In this situation, it usually makes sense to compile Thumb code and hand-optimise a few of the most CPU-intensive sections using full 32-bit ARM instructions, placing these wider instructions into the 32-bit bus accessible memory.

The first processor with a Thumb instruction decoder was the ARM7TDMI. All ARM9 and later families, including XScale, have included a Thumb instruction decoder.

VFP
VFP (Vector Floating Point) technology is a coprocessor extension to the ARM architecture. It provides low-cost single-precision and double-precision floating-point computation fully compliant with the ANSI/IEEE Std 754-1985 Standard for Binary Floating-Point Arithmetic. VFP provides floating-point computation suitable for a wide spectrum of applications such as PDAs, smartphones, voice compression and decompression, three-dimensional graphics and digital audio, printers, set-top boxes, and automotive applications. The VFP architecture also supports execution of short vector instructions but these operate on each vector element sequentially and thus do not offer the performance of true SIMD (Single Instruction Multiple Data) parallelism. This mode can still be useful in graphics and signal-processing applications, however, as it allows a reduction in code size and instruction fetch and decode overhead.

Other floating-point and/or SIMD coprocessors found in ARM-based processors include FPA, FPE, iwMMXt. They provide some of the same functionality as VFP but are not opcode-compatible with it.

Advanced SIMD (NEON)
The Advanced SIMD extension, marketed as NEON technology, is a combined 64- and 128-bit single instruction multiple data (SIMD) instruction set that provides standardized acceleration for media and signal processing applications. NEON can execute MP3 audio decoding on CPUs running at 10 MHz and can run the GSM AMR (Adaptive Multi-Rate) speech codec at no more than 13 MHz. It features a comprehensive instruction set, separate register files and independent execution hardware. NEON supports 8-, 16-, 32- and 64-bit integer and single-precision (32-bit) floating-point data and operates in SIMD operations for handling audio and video processing as well as graphics and gaming processing. In NEON, the SIMD supports up to 16 operations at the same time. The NEON hardware shares the same floating-point registers as used in VFP.

Acorn systems
The very first ARM-based Acorn Archimedes personal computers ran an interim operating system called Arthur, which evolved into RISC OS, used on later ARM-based systems from Acorn and other vendors.

Embedded operating systems
The ARM architecture is supported by a large number of embedded and real-time operating systems, including Windows CE, Symbian OS, FreeRTOS, eCos, INTEGRITY, Nucleus PLUS, MicroC/OS-II, QNX, RTXC Quadros, ThreadX and VxWorks.

Unix-like
The ARM architecture is supported by Unix and Unix-like operating systems such as GNU/Linux, BSD, Plan 9 from Bell Labs, Inferno, Solaris, Apple iOS, WebOS and Android.

Linux
The following Linux distributions support ARM processors:
 * Arch Linux
 * Ångström
 * Chrome OS
 * DSLinux
 * Debian
 * ELinOS
 * Fedora
 * Gentoo
 * GoboLinux
 * iPodLinux
 * Maemo
 * MeeGo
 * MontaVista
 * Slackware
 * T2 SDE
 * Ubuntu
 * webOS
 * Wind River Linux

BSD
The following BSD derivatives support ARM processors:
 * RISC iX (Acorn ARM2/ARM3-based systems only)
 * FreeBSD
 * NetBSD
 * OpenBSD
 * iOS

Solaris

 * OpenSolaris

Windows
Microsoft announced on 5 January 2011 that the next major version of the Windows NT family will include support for ARM processors. Microsoft demonstrated a preliminary version of Windows (version 6.2.7867) running on an ARM-based computer at the 2011 Consumer Electronics Show.Microsoft demonstrates early build of Windows 8