User:Hz98

Hardware Design Wiki
From now on, this Wikipedia page collects Hardware design books to share tips of hardware design for Protection Relay.

Here are few area that I am going to talk in this Wiki:

√ Hardware Design Process:

√ Common Circuitry Design:

√ Design Lesson and Learn:



Processor specifications
L1 cache size: 32 KB instruction; 32 KB data
 * Dual Cell BE Processors
 * PPE core: IBM® 64-bit Power Architecture™

L2 cache size: 512 KB  Local store: 256 KB   Registers: 128 x 128 bits wide 20 GB/s in each direction 1 GB 3.2-GHz XDR DRAM, 2 channels per processor 1 or 2 GB 667-MHz DDR2 organized as  2 VLP DIMMs per processor, 1 channel per DIMM Single-bit correct; double-bit detect on XDR and DDR2 Optional serial attached SCSI controller: 300 MB/s
 * SPEs: 8
 * EIB: 205 GB/s sustained aggregate bandwidth
 * Processor internal clock speed: 3.2 GHz
 * Processor-to-XDR-memory bandwidth: 25.6 GB/s
 * Processor-to-processor coherent interface
 * Memory
 * XDR Memory (each processor)
 * DDR2 memory (each processor)
 * ECC support
 * Flash: 32 MB
 * NVRAM: 1 MB
 * Storage
 * I/O Subsystems
 * Dual Gigabit Ethernet port connected to the midplane
 * Serial port: Via midplane to rear of chassis
 * Serial over LAN: Via BladeCenter Advanced Management Module
 * Expansion Option
 * High-speed daughtercard
 * InfiniBand 4X HCA expansion card
 * Companion Chip

AdvancedMC Card: RapidIO DSP and FPGA
Three TI TMS320TCI6482 DSPs: 1.2 GHz
 * Digital signal processors

Serial RapidIO interfaces: 1.25 Gb, 2.5 Gb, or 3.125 Gbps

JTAG/emulation support

2-wire EEPROM support

McBSP bus support

Code compatible with the TMS320C6455

RGMII Gigabit Ethernet supported on DSP_A and DSP_B

EMIF_A path from DSP_C to the FPGA

EMIF_A path from DSP_B to the FPGA SelectMAP to support reconfiguration Xilinx Virtex-4 FX100 (compatible with Xilinx Virtex-4 FX60)
 * Field-programmable gate array (FPGA)

Reconfigurable from Xilinx platform flash (XCF32P)

LVDS bus support

One 4x serial RapidIO interface to serial RapidIO switch

One 4x serial RapidIO/10-Gigabit Ethernet interface to AMC connector DDRII 250-MHz SDRAM per DSP: 64 MB
 * Memory

16-bit DDRII interface

Flash (DSP_A): 16 MB Tundra® Tsi578™ 8-port serial RapidIO switch
 * Serial RapidIO switch

Gbps support: 1.25, 2.5, and 3.125 FX100 FPGA performs Gigabit Ethernet PHY functions between AMC Ports 0 and 1 and DSP_A and DSP_B, respectively. Hitachi® HD64F2166 IPMI controller
 * Ethernet
 * IPMI

Voltage monitor

Geographical address monitor

Temperature monitors

Power/reset control

DSP and serial RapidIO switch EEPROM interfaces

FPGA and CFG CPLD interfaces Dual 10/100/1000 Ethernet (Ports 0-1)
 * AMC connector

4x serial RapidIO (Ports 4-7)

4x serial RapidIO or 10-Gigabit Ethernet port (Ports 8-11)

IPMB-A and IPMB-B link

Front panel

Per AMC.0, LEDs on front panel FPGA LVDS connector
 * Out of service: Red
 * User LED2: Green
 * User LED3: Yellow
 * Hot swap: Blue
 * DSP LED for each DSP
 * Two FPGA LEDs

JTAG debug connector

Reset push-button 14-pin front-panel JTAG/emulator/programming connector for DSPs and IPMI
 * Test and development

14-pin non-front-panel JTAG/emulator/programming connector for Xilinx FPGA and platform flash

4 AMC-specified LEDs

8 user-defined LEDs