User:Kapitaenk/sandbox

Jaguar architecture (Kabini and Temash)
In Jauary 2013 the Jaguar-based Kabini and Temash APUs were unveiled as the successors of the Bobcat-based Ontario, Zacate and Hondo APUs. The Kabini APU is aimed at the low-power, subnotebook, netbook, ultra-thin and small form factor markets, the Temash APU is aimed at the tablet, ultra-low power and small form factor markets. The 2-4 Jaguar cores of the Kabini and Temash APUs will feature numerous architectual improvements regarding power requirement and performance, such as support for newer x86-instructions, a higher IPC, a CC6 power state mode and clock gating. Kabini and Temash will be AMD's first, and also the the first ever quad-core x86 based SoCs. The integrated Fusion Controller Hubs (FCH) for Kabini and Temash are codenamed "Yangtze" and "Salton" repectively. The Yangtze FCH features support for two USB 3.0 ports, two SATA 6Gb/s ports, as well as the xHCI 1.0 and SD/SDIO 3.0 protocols for SD-card support. Both chips will feature DirectX 11.1-compliant GCN-based graphics as well as numerous heterogeneous system architecture (HSA) improvements. Both chips will be manufactured in 28 nm with a FT2 BGA package at TSMC and are expected to be released in the first half of 2013.

The Jaguar core will 3.1mm² at 28 nm, down from the bocat core size of 4.9mm² at 40 nm. The IPC of the jaguar based APUs is about 15% higher than their Bobcat based predecessors, 10% higher clocks are also possible without a power consumption increase. The new core design will add support for SSE4.1, SSE4.2, AES, PCLMUL, AVX, BMI, F16C, and MOVBE instruction sets, the memory address space has also been increased from 36 to 40 bits. Jaguar has been improved with a 128-bit floating point unit (FPU) with double-pumping support for 256-bit AVX instructions.

Power efficiency has been increased through clock gating and a new CC6 power state to reduce power requirements. The APUs will also include ARM A5 core with Trustzone security.