User:Konker3/Schottky Barrier Quantum Well Resonant Tunneling Transistor

A new transistor, Schottky Barrier Quantum Well Resonant Tunneling Transistor (SBQWRTT), was invented to continue the scaling trend as the MOSFET is approaching its fundamental scaling limits. This paper covers the device structure, device characteristics, and manufacturing process of the new device. This three-terminal device has a metal- semiconductor-metal-semiconductor-metal (MSMSM) structure forming a double-barrier quantum well. The current conduction mechanism is resonant tunneling, which produces a large driving current and a small swing. The SBQWRTT can be operated at lower VCC and consumes less power than the MOSFET. The SBQWRTT is a high-speed device because of its large driving current, small base width, quantum mechanical tunneling, ballistic transport of carriers, and low parasitic resistances. The SBQWRTT can be fabricated on silicon substrates for low cost and compatibility with today’s manufacturing infrastructure. The manufacturing process costs less than a CMOS process because of less photo masking steps. The current trends of increasing chip speed and functional density are difficult to maintain by the MOSFET. The SBQWRTT has the potential to become an important semiconductor device in the near future.

Introduction
In the past four decades, the integrated circuit industry has followed a dramatic path of shrinking device dimensions and increasing chip sizes, resulting in steady increases of performance and functionality. New generations of devices have appeared in every two to three years, following the so-called “Moore’s Law”. Each new generation has approximately reduced transistor size by 30%, increased circuit performance by about 40%, doubled logic circuit density, and quadrupled memory capacity comparing to the previous generation.

The MOSFET constitutes the fundamental building block of semiconductor technology. A large part of its success is due to the fact that it can be continuously scaled down to smaller dimensions while increasing circuit performance and lowering manufacturing cost. In order to maintain such rapid rate of improvement, aggressive scaling of MOS devices presents considerable challenges to the semiconductor industry. The major challenges include power consumption control, leakage current reduction, driving current improvement, thin gate insulators with high dielectric constant, metal gates with appropriate work functions, ultra-shallow source/drain junctions, parasitic resistance/capacitance reduction, statistical dopant fluctuation, and uniformity of device characteristics.

The most pressing limit to further miniaturization is the increase of power consumption. The power density at the chip surface is doubled for every 3.3 years. The rapid increase of heat generation is caused by insufficient reduction of power supply voltage and aggressive increase of transistor density. If the current trends in the clock frequency and the number of on-chip transistors continue, the power consumption of a high-performance microprocessor would reach 10 KW and the heat generation at the chip surface would reach 1000 W/cm2 within several years.

The industry generally expects that within a decade or so, MOSFET will encounter critical technological barriers and fundamental physical limitations to size reduction. Silicon technology has reached a point, at which significant innovations are required to circumvent the challenges associated with continued device scaling. There is a need for a new transistor device to continue the trends of increasing circuit performance, enhancing chip functionality, and lowering manufacturing cost.

Device Structure
Schottky Barrier Quantum Well Resonant Tunneling Transistor (SBQWRTT) is a three-terminal device having a metal-semiconductor-metal-semiconductor-metal (MSMSM) structure. A schematic drawing of an SBQWRTT is shown in Fig. 1. The three terminals are the emitter terminal, base terminal, and collector terminal. The MSMSM structure consists of emitter region, emitter barrier region, base region, collector barrier region, and collector region. The emitter, base, and collector regions are made of metals or silicides. The emitter and collector barrier regions are made of semiconductors. There are four Schottky barrier junctions in this structure. WB is the base width, WEB is the width of the emitter barrier region, and WCB is the width of the collector barrier region. When the structure is fabricated by epitaxial growth, the width of a region is the thickness of a layer.



Fig. 2 shows the band diagrams of an n-type SBQWRTT biased at (a) thermal equilibrium and (b) resonance. The SBQWRTT has two complementary device types, i.e. n-type and p-type, with primary carriers of electrons and holes, respectively. Two complementary device types are important in circuit design to reduce power consumption like CMOS. For an n-type SBQWRTT, qφbn is generally smaller than qφbp. For a p-type SBQWRTT, qφbp is generally smaller than qφbn. The SBQWRTT can be called an “H transistor” for short because the dumbbell shaped band diagram in Fig. 2(a) looks like the letter “H”.



Schottky junctions can be used to build heterostructures, similar to the heterostructures made of III-V compound semiconductors with different band gaps. The conduction band of an SBQWRTT forms a double-barrier quantum well. If WB is smaller than the de Broglie wavelength, the motion of electrons in the direction perpendicular to the Schottky junctions is quantized. Electrons can only have discrete energy values inside the quantum well. E1 is the ground state energy. It is found that E1 is dependent on WB but essentially independent of WEB and WCB.

Device Operation and Characteristics
The device operation and characteristics of n- and p-type SBQWRTTs are discussed below. The device attributes are shown in Table 1 unless they are set as variables. The devices are biased at VE = 0 V, VC = 0.2 V (n-type) or -0.2 V (p-type), and VCC = 0.2 V.

The device characteristics are dependent on barrier layer widths (WEB and WCB), base width (WB), and Schottky barrier heights SBH (qφbn and qφbp). Fig. 3(a) shows the electron transmission coefficient (TC) vs. energy for WEB = WCB = 13, 19, and 25 ML (monolayers) at VB = 0 V. TC can be obtained by solving the 1-D Schroedinger and Poisson equations. TC reaches its maximum of 100% when the energy of an injected electron is equal to E1, which is about 0.23 eV. TC decreases rapidly when E is deviated from the resonant energy, especially when barrier layers are thick. The resonance becomes blurred when the barrier layer thickness becomes very thin.

Fig. 3(b) shows the electron and hole tunneling currents, Jtn and Jtp, as functions of VB for WEB = WCB = 13, 19, and 25 ML. Jtn is the tunneling current of electrons from emitter to collector, and Jtp is the tunneling current of holes from collector to emitter. Jtn is proportional to TC multiplied by the occupation probability in the emitter and the unoccupied probability in the collector. Both Jtn and Jtp increase with decreasing WEB and WCB. For an n-type device, electrons are the majority carriers, and hole current is a leakage current.

Both Jtn and Jtp exhibit negative differential resistance (NDR) due to resonance tunneling. NDR can seriously degrade the driving current (Jon) and subthreshold swing (SS). As a general-purpose transistor, the device must be properly biased so that the NDR does not occur in normal circuit operation. For example, NDR occurs when VB > 0.23 V in Fig. 3(b). VCC can be set at 0.2 V to avoid NDR.

Fig. 3(c) shows SS (between VB = 0 and VCC) and Jon (= Jtn when VB = VCC) vs. WEB (= WCB). Jon increases monotonically with decreasing barrier layer thickness. SS reaches a minimum of 73.2 mV/dec when WEB = WCB = 19 ML. The minimal SS that can be achieved by the device at room temperature is kT/q·ln(10) = 60 mV/dec, which is controlled by the Fermi-Dirac distribution. SS increases rapidly with decreasing the barrier layer thickness. As the barrier layer thickness becomes very thin, the barrier layers cannot confine a quantum state in the quantum well, and the resonance becomes blurred. The optimal barrier layer thickness, WEB = WCB = 19 ML, is much smaller than the electron mean free path (MFP) of scattering in un-doped Si, so electrons can travel through the barrier layers without scattering. The barrier regions are preferred to be undoped to minimize the statistical dopant fluctuation and Coulomb scattering due to ionized impurities.

WB needs to be small to achieve high current gain and fast transistor switching speed. The electron density in a metal is high. The injected electrons in the base have a high rate of energy loss due to inelastic electron-electron scatterings. In a metal, the mean free time between collisions is about 50-100 fs [1] for electrons, which corresponds to MFP ≈ 50-100 Å (assuming the electron velocity is 107 cm/s). If WB is much smaller than MFP, most electrons injected from the emitter can traverse the quantum well ballistically and reach the collector. The base current is very small because very few carriers are recombined in the base.

Fig. 4(a) shows the electron TC vs. energy for WB = 1, 2, and 3 ML at VB = 0 V. Fig. 4(b) shows Jtn and Jtp as functions of VB for WB = 1, 2, and 3 ML. Fig. 4(c) shows SS and Jon vs. WB. The resonant energy is decreased with increasing WB as shown in Fig. 4(a). When WB increases from 1 to 2 ML, Jon is initially increased with decreasing E1 as shown in Fig. 4(c). When WB increases from 2 to 3 ML, E1 becomes smaller than 0.2 eV. Jon and SS are degraded due to NDR. A smaller WB can have a larger E1 and a wider operation range, but Jon may not be large enough if E1 is much larger than VCC. Therefore, E1 needs to be larger than VCC, but not by too much. Fig. 4(c) shows that WB has an optimal value of 2 ML, at which Jon is the largest and SS is the smallest.

Fig. 5(a) shows the electron TC vs. energy for qφbn = 0.24, 0.4, and 0.56 eV at VB = 0 V. Fig. 5(b) shows Jtn and Jtp as functions of VB for qφbn = 0.24, 0.4, and 0.56 eV. Fig. 5(c) shows SS and Jon vs. qφbn. When qφbn is reduced, E1 is decreased and Jon is increased. Jon reaches its peak when qφbn = 0.32 eV and E1 = 0.2 eV. If qφbn is further reduced, Jon starts to decrease and SS increases significantly due to NDR.

Ideally, an SBQWRTT can be an ambipolar device, operated as either an n- or a p-type transistor depending on the bias condition. The fabrication process can be simplified because only one type of device is to be fabricated. Since electrons have a higher effective Richardson constant and a smaller effective mass than those of holes, ambipolar devices with symmetric driving currents can be achieved if qφbn is slightly larger than qφbp. However, Fig. 5(c) shows Jon < 104 A/cm2 if qφbn > 0.56 eV (= Eg/2). In order to deliver the best performance for both types of devices, each device needs to be optimized individually.

The p-type SBQWRTT can have a device structure similar to the n-type SBQWRTT in Fig. 2(a), but with metal Fermi levels closer to the valance band, i.e. qφbp < qφbn. Fig. 6(a) shows Jtp and Jtn as functions of VB for WEB = WCB = 15 ML and qφbp = 0.2, 0.3, and 0.4 eV. When qφbp becomes smaller, E1 becomes smaller and NDR occurs at a smaller VB. Since holes have a smaller effective Richardson constant and a larger effective mass than electrons, qφbp needs to be smaller than 0.3 eV to improve hole driving current and suppress the electron leakage current. Fig. 6(b) shows SS vs. qφbp for WEB = WCB = 11, 15, and 19 ML. When qφbp is small, SS is seriously degraded by NDR.

Using Si/Ge heterojunctions in the barrier regions can solve the dilemma of driving current and swing for the p-type SBQWRTT. Fig. 7 shows the band diagrams of a p-type symmetric SBQWRTT biased at (a) thermal equilibrium and (b) resonance. The emitter barrier region, from left to right, is composed of a silicon layer with a thickness of WSi,1, a germanium layer with a thickness of WGe, and a silicon layer with a thickness of WSi,2. The conduction band and valence band offsets, DEC and DEV, are assumed to be 0.28 and 0.74 eV respectively at the Si and Ge interface.

Fig. 8(a) shows hole TC vs. energy for WGe = 10, 14, and 18 ML at VB = 0 V. Fig. 8(b) shows Jtp and Jtn vs. VB for WGe = 10, 14, and 18 ML. Fig. 8(c) shows SS and Jon vs. WGe. The Si/Ge/Si heterostructure forms a quantum well for holes. At some specific WGe such as WGe = 18 ML, TC has multiple peaks at different energies due to multiple quantum wells. When TC has multiple peaks, SS is degraded. Since Ge has a higher conduction band edge than Si, increasing WGe can effectively block the electron leakage current. In the WGe range of interest, Jon has two peaks roughly at WGe = 5 and 15 ML. Fig. 8(c) shows SS is roughly minimal when Jon becomes maximal.

Fig. 9(a) shows hole TC vs. energy for WSi,2 = 6, 9, and 12 ML at VB = 0 V. Fig. 9(b) shows Jtp and Jtn vs. VB for WSi,2 = 6, 9, and 12 ML. Fig. 9(c) shows SS and Jon vs. WSi,2. Both Jtp and Jtn increase with decreasing WSi,2. When the barrier layers are very thin, the TC curve becomes fairly flat such as the curve of WSi,2 = 6 ML in Fig. 9(a). Holes of a wide energy range can tunnel through the double-barrier quantum well with a high probability. The resonant tunneling effect is weakened and SS is degraded when WSi,2 is very small.

From the simulation results above, the optimal device structures are shown in Table I, and their device characteristics are shown in Table II.

It was commonly thought that there is a high density of interface states at the metal/semiconductor junction that pin the Fermi level, so that SBH does not have a strong dependence on the metal work function. This mechanism did not suggest the dependence of SBH on the atomic structure of the metal/silicon interface. However, many recent experiments suggest the Fermi level is not pinned and the interface structure plays an important role in the formation of SBH. The best known example is the dependence of the SBH on silicide orientation at the NiSi2-Si(111) interface. Two orientations of NiSi2 can be grown on Si(111): type A, in which the silicide has the same orientation as the substrate, and type B, in which silicide shares the surface normal axis with Si but is rotated 180° about this axis with respect to the Si. The SBH of NiSi2 on n-type Si(111) is 0.65 eV for type A orientation and 0.79 eV for type B orientation. Another example is the SBH of NiSi2/Si(100) junction is 0.4 eV, which is very different from the value of 0.6-0.7 eV usually observed from polycrystalline nickel silicides on n-type Si(100).

Circuit Performance and Layout
Fig. 10(a) shows Jtn and Jtp vs. VB at two different VC for the n- and p-type SBQWRTTs as specified in Table 1. Jt increases exponentially with VB for VB within the VCC range. Fig. 10(b) shows the Jt-VC characteristics for the n- and p-type SBQWRTTs. Jon of the n-type device is about 70% larger than that of the p-type device. Jtn increases continuously with VC and never saturates, while Jtp becomes saturated with VC when |VC| > 0.1 V. The p-type SBQWRTT has a Si/Ge/Si heterojunction in the barrier region. For both n- and p-type devices, the Jt-VC curves are further spaced apart with increasing VB. The transfer curve and circuit diagram of an SBQWRTT inverter are shown in Figs. 10(c) and 10(d). The p-type SBQWRTT is 50% larger than the n-type SBQWRTT to compensate its lower driving current. Despite of so many differences in the device structure, operation mechanism, and device characteristics between SBQWRTTs and MOSFETs, the SBQWRTT inverter shows a balanced transfer curve and large output/input gain.

Fig. 11 shows the layout of an inverter circuit consisting of an n-type SBQWRTT and a p-type SBQWRTT. The n-type SBQWRTT is stacked on top of the p-type SBQWRTT to save area. The n-active area defines the top (i.e. collector) electrode area, and the n-base area defines the mid and bottom (i.e. base and emitter) electrode areas for the n-type SBQWRTT. The p-active area defines the top (i.e. emitter) electrode area, and the p-base area defines the mid and bottom (i.e. base and collector) electrode areas for the p-type SBQWRTT. The p-active area is larger than the n-active area in order to have balanced driving currents between the n- and p-type devices. The inverter’s input connects to the base contacts of the n- and the p-type SBQWRTTs. The inverter’s output connects to the collector contacts of the n- and the p-type SBQWRTTs. The n-type SBQWRTT’s emitter contact connects to ground. The p-type SBQWRTT’s emitter contact connects to VCC.

Fabrication Process
A proposed manufacturing process is described below. Fig. 12(a) shows the layer structure of the inverter in Fig. 11. Fig. 12(b) shows the cross-sectional view of the inverter taken along the B-B’ line in Fig. 11. Surface preparation and film growth is performed in an ultra-high vacuum (UHV) deposition chamber with a base pressure of < 4×10-11 Torr. The starting material is a Si (100) wafer.

An epitaxial CaF2 film with a thickness of 200-400 Å is grown by electron beam evaporation of CaF2 source onto the wafer kept at 400-650°C. The film is then rapid thermal annealed at 600-850°C to reduce interface charge density. The lattice constant of CaF2 is nearly equal to that of Si (mismatch of 0.6%). The insulating CaF2 film provides device isolation between the devices above and below. After CaF2 growth, wafer temperature is lowered to less than 100°C and a thin Si layer (20-60 Å) is deposited on the wafer. The wafer is heated up to 600°C to complete solid phase epitaxy (SPE) of the pre-deposited Si layer. An epitaxial Si layer about 100-200 Å thick is grown by MBE at a substrate temperature of 550-750°C.

NiSi2 and CoSi2 have cubic lattice structures and are closely lattice matched to silicon (mismatch of -0.4% for NiSi2 and –1.2% for CoSi2). Single-crystal silicide films of NiSi2 and CoSi2 can be epitaxially grown on Si substrates under UHV conditions by MBE and atomic layer deposition (ALD) with atomically abrupt and structurally perfect interface. These silicide films have good electrical and mechanical properties such as good layer uniformity, high electrical conductivity, and excellent thermal stability. Single-crystal silicon layers can be epitaxially grown on top of the silicide films under UHV conditions by MBE and ALD. In this process, ALD and MBE are integrated in a UHV deposition chamber to grow different layers with different thickness requirements.

A CoSi2 film, as the collector of a p-type SBQWRTT, is grown on wafer in a UHV MBE chamber using a two-step template method [3]. First, a template layer about 10 Å thick is grown by stoichiometric co-deposition of Co and Si at room temperature, and annealed in situ under vacuum at 400°C for 1 min. Following the growth of a thin CoSi2 template, a thicker CoSi2 film is grown by co-deposition of Co and Si at a substrate temperature of 450°C to a final total thickness of 200-400 Å.

A Si/Ge/Si composite film, as the collector barrier of a p-type SBQWRTT, is epitaxially grown on the wafer. The composite film consists of 2 ML of Si, 14 ML of Ge, and 9 ML of Si, which are sequentially deposited by ALD at a substrate temperature of 200°C. The composite film is then annealed at 700°C for 2 min.

A CoSi2 film with a thickness of 2 ML, as the base of a p-type SBQWRTT, is grown on the wafer by ALD at a substrate temperature of 200°C, and annealed at 400°C for 1 min. A Si/Ge/Si composite film, as the emitter barrier of a p-type SBQWRTT, is grown on the wafer under the same growth condition as the collector barrier layer. The Si/Ge/Si composite film consists of 9 ML of Si, 14 ML of Ge, and 2 ML of Si. A CoSi2 film, as the emitter of a p-type SBQWRTT, is grown on the wafer under the same growth condition as the collector.

A Si buffer layer is epitaxially grown by MBE by using the Si template technique as before. A CaF2 film is epitaxially grown on the wafer under the same growth condition as before. This CaF2 film provides device isolation between the n-device above and the p-device below. A Si buffer layer is epitaxially grown on the wafer under the same growth condition as the prior Si buffer layers.

A NiSi2 film, as the emitter of an n-type SBQWRTT, is grown on the wafer in a UHV MBE chamber using a two-step template method [3]. First, a thin NiSi2 template layer about 25 Å thick is grown by stoichiometric co-deposition of Ni and Si at room temperature, followed by annealing at 500°C for 2 min to induce the epitaxial growth of NiSi2. Ni and Si are then co-deposited at room temperature onto this template layer to a final total thickness of 200-400 Å with a subsequent high-temperature anneal at 750°C for 2 min to improve the crystal quality of NiSi2 film.

A Si layer with a thickness of 19 ML, as the emitter barrier of an n-type SBQWRTT, is grown on the wafer by ALD at a substrate temperature of 200°C and annealed at 700°C for 2 min. A NiSi2 film with a thickness of 2 ML, as the base of an n-type SBQWRTT, is deposited on the wafer by ALD at a substrate temperature of 200°C and annealed at 800°C for 1 min. A Si layer with a thickness of 19 ML, as the collector barrier of an n-type SBQWRTT, is grown on the wafer. A NiSi2 film with a thickness of 200-400 Å, as the collector of an n-type SBQWRTT, is grown on the wafer. A SiO2 layer with a thickness of about 500 Å is deposited on the wafer for passivation. The wafer is then removed from the UHV chamber.

In the exemplary layout and process flow, the SBQWRTT has a vertical structure formed by epitaxial growth. The n-type SBQWRTT is stacked on top of the p-type SBQWRTT to save area. Both n- and p-type devices have three silicide electrode layers for the collector, base, and emitter. From top to bottom, the three electrode layers are collector/base/emitter for the n-type SBQWRTT and emitter/base/collector for the p-type SBQWRTT. In digital circuits, the emitters of n-type SBQWRTTs are sometimes connected to ground and the emitters of p-type SBQWRTTs are sometimes connected to VCC. To minimize small signal coupling between the two devices, the bottom electrode of an n-type SBQWRTT and the top electrode of a p-type SBQWRTT are emitters. It is also possible to insert a ground plane, made of epitaxial silicide, between two emitter layers to further reduce AC coupling.

As shown in Fig. 12(b), mesas are formed to provide area for contact landing and device isolation between neighboring devices. The n-active area defines the n-top electrode mesa. The n-base area defines the n-base mesa. The p-active area defines the p-top electrode mesa. The p-base area defines the p-base mesa. Photolithographic process and highly selective wet etch are used in mesa formation. The n- and p-base areas define not only the areas of base layers but also the areas of bottom electrode layers. After the mesa formations, an inter-level dielectric (ILD) layer of SiO2 is deposited by low-pressure chemical vapor deposition (LPCVD) on the wafer, and processed by chemical mechanical polishing (CMP) to achieve global planarization.

The contact to each electrode layer has its own photo mask and contact etch. There are 6 contact masks for 6 electrode layers. Si3N4 sidewall spacer is formed in the contact hole to the bottom electrodes by conformal deposition and anisotropic etch. The sidewall spacer provide self-aligned insulation between the contact plug and the above base electrode layer. If sidewall spacer is not used, two additional masks will be needed to create mesas for two bottom electrode layers. Since the base layers are atomically thin, the semiconductor barrier layers are used as etch stop in base contact etch. Tungsten is deposited to fill in the contact hole. CMP is used to achieve global planarization. Low-k dielectric is deposited, patterned, and etched to create trenches for metal-1. Copper is deposited and polished to form the metal-1 layer.

Advantages Over MOSFET
The SBQWRTT has the following advantages over the MOSFET attributed to its simple device structure and current conduction mechanism of resonant tunneling.


 * 1) Smaller transistor size -- The SBQWRTT has a smaller transistor size and a higher packing density. The minimum device size is determined by the contact size and contact-to-contact space that can be provided by photo and etching processes. The SBQWRTT is a three-terminal device, and typically has a compact rectangular shape in layout. N- and p-type devices can occupy the same active area with one stacking on top of the other to save area.
 * 2) Higher speed -- The SBQWRTT can operate at a much higher speed because of its large driving current, small base width, quantum mechanical tunneling, ballistic transport, and low parasitic resistances. The intrinsic speed of a tunneling device is much faster than a device such as FET or BJT operating on drift or diffusion process. The emitter/base/collector regions of an SBQWRTT are made of low-resistance metals or silicides. The barrier regions are undoped to eliminate the impurity scattering.
 * 3) Lower power consumption -- The SBQWRTT can operate at a lower power supply voltage and consumes less energy. A small swing is the key for low VCC. The current conduction mechanism is resonant tunneling. TC is high at resonance, and drops by orders of magnitude if the energy is slightly off the resonant energy. The SBQWRTT can be turned on and off in a small voltage range.
 * 4) Better device uniformity -- Variations of device characteristics are much smaller because statistical dopant fluctuation and line edge roughness (LER), which are two major sources of device variations in the MOSFET, do not exist in the SBQWRTT.
 * 5) Lower manufacturing cost -- SBQWRTTs can be fabricated on silicon substrates for low cost and compatibility with today’s manufacturing infrastructure. The SBQWRTT fabrication process is simpler and costs less because less photo masking steps are used and there are no requirements of ultra-shallow junctions, high-k metal-gate stack, embedded SiGe S/D, and dual stressor layers. The SBQWRTT does not require photolithography to define its critical dimensions. Active layers are grown by epitaxy with precise thickness control.

Prior Art Devices
Two prior-art devices, metal base transistors (MBT) and conventional resonant tunneling transistors (RTT), both operating on the principle of quantum mechanical tunneling, are to be discussed.

The metal base transistor was an early attempt to achieve better performance than bipolar transistors. The device structure of the MBT has three different versions: (a) metal-insulator-metal-insulator-metal (MIMIM) structure, (b) metal-insulator-metal-semiconductor (MIMS) structure, and (c) semiconductor-metal-semiconductor (SMS) structure. All of them have metal for the base. For the MBTs having MIMIM and MIMS structures, when the device is properly biased, electrons are injected from the emitter to the base by tunneling through a thin insulating barrier. The injected electrons are called hot electrons since they have energies more than a few kT above the Fermi level in the base. The MIMIM device is also one of the hot-electron transistors and ballistic injection transistors. The hot electrons continue to travel through the base to the collector if they are not recombined in the base. The SMS MBT employs thermionic emission rather than tunneling injection of hot carriers into the base because the Schottky junction has smaller emitter-to-base barrier height than the MIM structure. Early MBTs have been plagued by two major problems, which are the poor base transport factor aT due to their relatively large base widths and the difficulty of growth of good-quality single-crystal semiconductor materials on metals. Because of these problems, there has been very little development on the MBT in recent years.

The SBQWRTT is different from the MBT in at least the following fundamental aspects:


 * 1) The MBT has no Schottky junction in the MIMIM structure, one Schottky junction in the MIMS structure, and two Schottky junctions in the SMS structure. While the SBQWRTT has four Schottky junctions in the MSMSM structure.
 * 2) For the MBT with either MIMIM or MIMS structure, the emitter barrier is an insulator. For the MBT with either MIMS or SMS structure, the collector region is not atomically thin and heavily doped near the collector contact. While the SBQWRTT has two semiconductor barriers, i.e. emitter barrier region and collector barrier region. The two barriers are atomically thin and typically undoped to minimize statistical dopant fluctuation and impurity scattering.
 * 3) The MBT with either MIMIM or MIMS structure allows current to flow through its insulating barrier, creating a reliability issue due to hot carrier injection. While the SBQWRTT has no insulator in its current path.
 * 4) The MBT does not operate in the principle of resonant tunneling. The device is typically biased so that the injected electrons have energies much above the Fermi level in the base. Since the discrete energy levels in the base are closer at a higher energy, the injected hot electrons almost have continuous energy levels. On the other hand, the SBQWRTT typically has a single energy state in the quantum well. The driving current is enhanced by resonant tunneling as injected electrons having energies close to the first discrete energy level in the quantum well.

The conventional RTT uses quantum effects to produce NDR. The device has a double-barrier quantum-well structure typically formed by the heterojunctions of III-V compound semiconductors (such as GaAs and AlGaAs) with large discontinuities in the conduction band. The electron energy in a quantum well is quantized. Resonance occurs when the injected electrons have certain energies coincide with the energies of the quasi-bound states in the quantum well. The tunneling current decreases when the energy deviates from the discrete energy levels. This leads to NDR in the I-V characteristics. This effect can be used for microwave generation and amplification.

Although both SBQWRTT and conventional RTT have double-barrier quantum-well structures, they are fundamentally different in device structure and operation mechanism.


 * 1) The quantum well region is a semiconductor for a RTT, while the quantum well region is a metal or silicide for an SBQWRTT.
 * 2) The RTT has no Schottky junctions, while the SBQWRTT has four Schottky junctions in its MSMSM structure.
 * 3) The RTT is mainly used in circuit applications such as oscillators because of its NDR. The device is typically biased between the peak and valley points. On the other hand, the SBQWRTT is a general-purpose transistor and typically biased below the peak point to avoid NDR. In a general circuit application, NDR could cause unwanted oscillation and driving current reduction.
 * 4) The RTT typically has multiple energy levels in the quantum well, so the I-V characteristics show multiple peaks. On the other hand, the SBQWRTT typically has a single energy state in the quantum well. The I-V characteristics of an SBQWRTT are similar to those of conventional transistors such as BJTs and MOSFETs without multiple peaks.