User:Minhminh23394/sandbox

•	Verilog code for First-In First-Out (FIFO) memory http://www.fpga4student.blogspot.com/2016/12/what-is-fpga-five-reasons-why-i-love-fpga.html http://www.fpga4student.blogspot.com/2017/01/verilog-code-for-fifo-memory.html •	Verilog code for 16-bit single cycle MIPS processor http://www.fpga4student.blogspot.com/2017/01/verilog-code-for-single-cycle-MIPS-processor.html •	Programmable digital delay timer (LS7212) in Verilog HDL http://www.fpga4student.blogspot.com/2017/01/programmable-digital-delay-timer-in-Verilog.html •	Basic digital logic components in Verilog HDL http://www.fpga4student.blogspot.com/2017/01/basic-digital-blocks-in-verilog.html •	32-bit Unsigned Divider in Verilog http://www.fpga4student.blogspot.com/2016/12/32-bit-unsigned-divider-in-verilog.html •	Fixed-Point Matrix Multiplication in Verilog[Full code+Tutorials] http://www.fpga4student.blogspot.com/2016/12/fixed-point-matrix-multiplication-in-Verilog.html •	Verilog Implementation of Plate License Recognition on FPGA http://www.fpga4student.blogspot.com/2016/11/plate-license-recognition-verilogmatlab.html •	Parameterized Carry-Look-Ahead Multiplier on FPGA using Verilog HDL http://www.fpga4student.blogspot.com/2016/11/verilog-code-for-carry-look-ahead-multiplier.html •	Verilog implementation of a Microcontroller (Part 3- Verilog code) http://www.fpga4student.blogspot.com/2016/11/verilog-code-for-microcontroller.html •	Verilog code for 4x4 Multiplier using two-phase self-clocking system http://www.fpga4student.blogspot.com/2016/11/verilog-code-for-4x4-multiplier-using.html •	Verilog code for a parking system using Finite State Machine (FSM) http://www.fpga4student.blogspot.com/2016/11/verilog-code-for-parking-system-using.html •	Image processing on FPGA using Verilog HDL http://www.fpga4student.blogspot.com/2016/11/image-processing-on-fpga-verilog.html •	Two ways to load a text file into FPGA or the initial values to a memory in Verilog/ VHDL (synthesizable) http://www.fpga4student.blogspot.com/2016/11/verilog-code-for-traffic-light-system.html •	Verilog code for Traffic light controller http://www.fpga4student.blogspot.com/2016/11/verilog-code-for-traffic-light-system.html •	Verilog code for Alarm clock on FPGA http://www.fpga4student.blogspot.com/2016/11/verilog-code-for-alarm-clock-on-fpga.html •	VHDL code for FIFO Memory •	http://www.fpga4student.blogspot.com/2017/01/vhdl-code-for-fifo-memory.html •	A low pass FIR filter for ECG Denoising in VHDL •	http://www.fpga4student.blogspot.com/2017/01/a-low-pass-fir-filter-in-vhdl.html •	What is an FPGA? Top five reasons why I love FPGA design •	http://www.fpga4student.blogspot.com/2016/12/what-is-fpga-five-reasons-why-i-love-fpga.html •	A complete 8-bit Microcontroller in VHDL •	http://www.fpga4student.blogspot.com/2016/12/a-complete-8-bit-microcontroller-in-vhdl.html •	[Full VHDL code] Matrix Multiplication Design using VHDL and Xilinx Core Generator •	http://www.fpga4student.blogspot.com/2016/11/matrix-multiplier-core-design.html •	Parameterized N-bit switch tail ring counter (VHDL behavior and structural code with testbench) •	http://www.fpga4student.blogspot.com/2016/11/programmable-n-bit-switch-tail-ring.html •	VHDL code for digital clock on FPGA •	http://www.fpga4student.blogspot.com/2016/11/vhdl-code-for-digital-clock-on-fpga.html •	VHDL code for the 8-bit 74F521 Identity Comparator •	http://www.fpga4student.blogspot.com/2016/11/verilog-code-for-8-bit-74f521-identity.html •	Two ways to load a text file into FPGA or the initial values to a memory in Verilog/ VHDL (synthesizable) •	http://www.fpga4student.blogspot.com/2016/11/two-ways-to-load-text-file-to-fpga-or.html