User:Nepalvlsi

Low power vlsi design and optimization for speed and area: Contribution by Ritu Raj lamsal:::: This is My area for Ph.D Research.

Performance oriented Low power CMOS VLSI design Techniques. With the invention of solid state semiconductor device around late 1940’s the world of semiconductor technology has been drastically picked up. This phenomenal achievement is due to the improvement in technology in various aspects. Tens of millions of transistor in a single integrated circuit is now made possible due to improvement in semiconductor physics, manufacturing technology, computer aided Design tools and various software’s. Scientist and technologist predict that this train of VLSI design continues for next 15 -20 years until the miniaturization is reached. We have seen that Discrete electronic components is replaced by the integrated circuit, application oriented chips Application specific integrated circuits (ASIC’s) are fabricated, Systems are now build in a system on chip (SOC). However, there is now a major challenging issue for the designers regarding the power consumption and optimal performance of VLSI design. Designer have drifted from bipolar technology to CMOS Technology especially for digital design to address the power consumption problem and succeeded  to large extend where the number of gates count in a integrated circuit was moderate. As the technology is scaling further the major concern of Area constraint in early years now become diluted by new emerging power constrained. For example if a single transistor consumes very small say 10 microwatt and suppose a integrated circuit contains 10 millions such transistor roughly overall power consumption is 100 watt. This results in need of introducing a cooling system with more area and cost. Most importantly there has now become a huge requirement for saving power due to mobile, sensors; wireless and hand held devices since these devices are portable and generally powered by battery source. The life of battery is a major area of concern. The performance of the device depends on major three important factors as Area, Speed, Power .As mentioned above Area is now not a constrained as the devices are scaling down, for better speed of the device the old methods of increasing  the clock frequency now has to be addressed  together with the power consumption as it is obvious  that high switching  needs more power  hence the major field of study is now to find optimum performance of the device with low power consumption .Another difficulties for the designer to obtain high speed is question by the routing problem which  needs a large amount of interconnection and introduces a significant time delay. For the optimal performance the power, delay relation has to be analyzed. The RC product introduced by the interconnection and formation of parasitic resistor and capacitor affects the performance of the device. The golden power, delay equation shows that  P= 1/2.C .V2. F. From the above equation, it is clear that power is directly proportional to capacitance, switching frequency and more interestingly, power has square relation with supply voltage. For less power consumption in the beginning it might suggest that the supply voltage and switching frequency can be decreased but it has an adverse effect on performance. Therefore, it is a major concern to find the optimum relation between power and device performance. 	         CMOS circuit dissipates the power in the form of Static and Dynamic power dissipation. Static power dissipation is mainly due to reversed biased current and subthreshold current. The total static power dissipation can be written as the summation of leakage current * supply voltage. Dynamic power dissipation occurs when there is a transition of logic .this dissipation is due to the Charging and discharging of the load capacitance and Short circuit current.Capacitor Charging/discharging constitute  (85-90% of active power).Energy is ½ CV2 per transition. Short-Circuit Current (When both p and n transistors turn on during signal transition constitute of (10-15% of active power).Sub threshold Leakage (dominates when inactive) Transistors don’t turn off completely. formation of parasitic source and drain diodes leak to substrate.  So overall power dissipation in CMOS circuit is P total = P(static) + P (charging/discharging) + P(short circuit). Low power CMOS VLSI design aims to reduce these power dissipation using various design techniques and physics.         To address this issues various techniques are  adapted in various level of design hierarchy, for example in circuit level which deals with individual  transistor and their dimensions designers uses the analytical  method called logical  effort for sizing the transistor for relatively simple custom design for minimizing the delay. However for complex circuits with multiple paths and interconnect parasitics it becomes impractical for manual sizing and no analytical approach is available. In the gate level, commercial CAD tools are used for technology mapping to choose the gates of different size to meet the delay target but it does not guarantee the optimum design. Various design techniques can be introduced at various level of design hierarchy, starting from fabrication technology, circuit design,microarchitectura,instruction set,and software level. Which ultimately yields the optimum design for all parameters like power, speed and Area. With the available CAD design tools and HDL software’s in different level of abstraction we can verify the performance under the power constrained design. The above description suggests that there is a huge scope of research in the field of low power VLSI circuits design techniques especially for portable devices where proper balancing between power consumption and performance is required. Signature of Candidate. Ritu RAj Lamsal