User:Oli~enwiki/Architecture Project

Head
This my architecture project memo consisting mainly three parts.
 * Schedule is the plan of my project.
 * Progress contains what I learn, what I see, what I hear, what I think and most important what I do.
 * The remainder is the details of my project.

My english is very poor. I forced myself to write this document in english to improve my written english. Forgive my mistakes in the texts.

 Created at 19:30, April 14th 2006

Schedule
The google page now is too poor to create forms.

to be made...

Progress

 * Study the implementation of MIPS cpu in a Japanese profecessor named Yamin Li. The most terrible thing is that all are accomplished by graphical files using Maxplus. It means that the cpu is built up by individual elements!! -- March 14th, 2006


 * want to implement an ALU but meet many problems -- March 14th, 2006

Background
This semester I have a lesson called Computer Architecture, with the textbook Computer Organization & Design: The Hardware/Software Interface. The teacher is a lovely man named Alei Liang, who has his time before college in the city, Bengbu, the same with me, but his native place is in Fujian Province.

This lesson mainly talks about the CPU architecture of MIPS. From the history of the CPU to the basic architecture of PC, from the introduction of assembly language to Memory Hierarchy are all mentioned in this lesson.

The hard work of the lesson is the project to implement a reduced MIPS cpu with hardware description language. It doesn't have definite demand. The score of project accomplishing pipeline with data hazards being resolved will be surely high.

I haven't started my work now. So I don't know how many facilities I can get. In fact, I strongly want to implement the Tomasulo's feature. I know it is very hard.

The tool I will use is Quartus and I will us Verilog HDL. Some of my classmates want to use SystemC. I don't use it because I want to learn a hardware description language through this project.

There must be a lot of phases through my implementing the project. I haven't made a schedule now. But the first I should do is learning the verilog language without question.

 Created at 16:40, April 14th 2006

Phase 1: Learning VerilogHDL
Days ago I have briefly read some book on Verilog discontinuously. But now I must learn to use it systemly.

Today I have begun my approach. Through writing an ALU, I practised to use verilog. The source of the ALU is found in the introduction of Quartus for verilog user. During the work, some problems haven't thought about before appear one after anther. like how many clock cycles does this ALU use to accomplish one operation, why it will us registers inner the ALU to save the input and so on. Although these problems reduce my positivity seriously, I know I must think more.

 Created at 17:07, April 14th 2006