User:P30mehrdad

Mostafa Ersali Salehi Nasab

Short Biography: Mostafa Salehi is a PhD candidate at University of Tehran, Iran. He received a BS degree in electrical and computer engineering from the University of Tehran, Tehran, Iran, in 2001, and a master's degree in computer engineering from The Amirkabir University of Technology in 2003. His research interests include computer architecture, network processors, embedded systems, and high-performance and low-power architectures for digital systems.

Education : 2004 – Now: PhD candidate, Computer Engineering, University of Tehran, Tehran Thesis Title:        Design of a High-Performance Network Processor Advisor:             Prof. S. Mehdi Fakhraie, email: fakhraie@ut.ac.ir 2001 _ 2003: M. Sc., Computer Engineering, Amirkabir University of Technology, Tehran Thesis Title:        Design of an Asynchronous RISC Processor for Contactless Smart Cards Advisor:             Prof. Hossein Pedram, email: pedram@aut.ac.ir 1997 – 2001:   B. Sc., Electrical and Computer Engineering, University of Tehran, Tehran Project Title:        Modeling the V8uRISC Microprocessor in VHDL and Testing it under HW/SW Platforms Advisor:               Prof. Zainalabedin Navabi, email: navabi@ece.neu.edu 1995 – 1997:  Diploma, Mathematics and Physics, Allameh High School, Kerman

Research Interests: · Computer Architecture: Parallel, High-Performance, and Low-Power Architectures

· Embedded Systems: Embedded Processors, HW/SW Co-Design

· Network Systems: Network and Packet Processors

Research Experience: 2004 – Now: Research Assistant, Silicon Intelligence Lab., School of ECE, University of Tehran, Iran.

·  Design of a high-performance network processor.

2001 – 2003 : Research Assistant, Async Lab., Computer and IT Department, Amirkabir University of Technology, Iran.

·  Contributing to design of PERSIA, a synthesis and layout design tools for asynchronous circuits.

·  Design of an asynchronous RISC processor for contactless smart cards.

1997 – 2001: Research Assistant, CAD Lab., School of ECE, University of Tehran, Iran.

·  Modeling the V8uRISC microprocessor in VHDL.

Work Experience: 2000 – 2002:       Emad Semiconductor, Tehran, Iran.

·       Design, modeling, implementation and testing the chip of RSA cryptosystem algorithm.

·       Research in CAN and VAN in-vehicle network protocols.

·       Research in GPS systems.

·       Implementation of GSM 11.17 test procedure.

2002 – 2004:       Amirkabir University of Technology, Tehran, Iran.

·       Design and implementation of a hardware accelerator PCI board for a VPN system, supporting RIJNDAEL, TDES cryptosystem and MD5, SHA1 message digest algorithms.

·       Design and implementation of a 32-bit RISC processor on FPGA.

2004 – 2005:        Parse Semiconductor, Tehran, Iran

·       Design and implementation of a 32-bit RISC processor based on SPARC architecture.

2005 – Now:       SiNA Semiconductor, Tehran, Iran

·       Design and implementation of a 32-bit special purpose RISC for network processors.

Publications: M. E. Salehi, R. Rafati, F. Baharvand, and S. M. Fakhraie, "A Quantitative Study on Layer-2 Packet Processing on a General Purpose Processor," In proceedings of the International Conference on Microelectronic, ICM 2006. M. E. Salehi, A. Hormati, A. Banaiyan, and S. M. Fakhraie, “A Proposed Architecture for Layer-2 Packet Processor,” In proceedings of the Iranian Conference on Electrical Engineering, ICEE 2007. M. Najibi, M. Salehi, A. Afzali Kusha, M. Pedram, S. M. Fakhraie, H. Pedram, “Dynamic Voltage and Frequency Management Based on Variable Update Intervals for Frequency Setting”, In proceedings of International Conference on Computer Aided Design, ICCAD 2006. M. Salehi, M. Najibi, A. Afzali Kusha, M. Pedram, S. M. Fakhraie, H. Pedram, “Implementation of a Dynamic Voltage and Frequency Management In a Low-Power Processor”, In proceedings of the Iranian Conference on Electrical Engineering, ICEE 2006. M. Salehi, K.saleh, H. Kalantari, M. Naderi, H. Pedram, "High-Level Energy Estimation of Template-Based QDI Asynchronous Circuits Based on Transition Counting" In proceedings of the 16th International Conference on Microelectronics, ICM 2004 M. Salehi, H. Pedram, M. Saheb Zamani, M. naderi, “A Transistor-Level Placement Tool for Asynchronous Circuits”, In proceedings of the Computer Society of Iran Computer Conference, CSICC2004. M. Khajooyi, M.Salehi, F. Soheili, H. Torabi, “New VLSI Design for Hardware Implementation of RSA Cryotosystem Algorythm”, in proceedings of the Iran Telecommunication and Research Center, ITRC2000.

http://khorshid.ut.ac.ir/~salehi/