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= SHAKTI - The First Indigenous Indian Microprocessor & Microcontroller. = SHAKTI is the first opensource initiative by the Reconfigurable Intelligent Systems Engineering (RISE) group at Indian Institute of Technology, Madras to develop the first indigenous industrial-grade processor. The aim of SHAKTI initiative includes building an opensource production-grade processor, complete System on Chips (SoCs), development boards and SHAKTI based software platform. The primary focus of the team is architecture research to develop SoCs, which is competitive with commercial offerings in the market concerning area, power and performance. All the source codes for SHAKTI are open-sourced under the Modified BSD License of the University of California, Berkeley. The project was funded by Ministry of Electronics and Information Technology (MeITY), Government of India.

Processors
SHAKTI processors are based on the RISC-V ISA. The processors are based on 22nm FinFET technology. SHAKTI has envisioned a family of processors as part of its road-map, catering to different segments of the market. They have been broadly categorized into "Base Processors", "Multi-Core Processors" and "Experimental Processors". The E and C-classes are the first set of indigenous processors aimed at Internet of Things (IoT), Embedded and Desktop markets. The processor design is free of any royalty and is open-sourced under the Modified BSD License.

The SHAKTI project aims to build 6 variants of processors based on the RISC-V ISA.

E-class
The E-class is 32/64 bit microcontrollers capable of supporting all extensions of RISC-V ISA, aimed at low-power and low compute applications. The E-class is an In-order 3 stage pipeline having an operational frequency of less than 200MHz on silicon. It is positioned against ARM’s M-class (CorTex-M series) cores. It's capable of running real-time operating systems like FreeRTOS, Zephyr and eChronos. Market segments of E-class processor support Smart-cards, IoT devices, motor controls and robotic platforms.

E-arty35T is an SoC built around E-class. The E-arty35T SoC is a single-chip 32-bit E-class microcontroller with 128kB RAM. It has 32 General Purpose Input Output (GPIO) pins (out of which upper 16 GPIO pins are dedicated to onboard LEDs and switches), a Platform Level Interrupt Controller (PLIC), a Counter, 2 Serial Peripheral (SPI), 2 Universal Asynchronous Receiver Transmitter (UART), 1 Inter-Integrated Circuit (I2C), 6 Pulse Width Modulator (PWM) and an inbuilt Xilinx Analog to Digital Converter( X-ADC).

C-class
The C-class is a 64-bit controller class of processor, aimed at mid-range embedded application. The core is highly optimized, 6-stage in-order design with MMU support and capability to run operating systems like Linux and Sel4. It's extremely configurable with the support of the standard RV64GC ISA extensions. It targets the mid-range compute systems running over 200-800MHz. It can also be customized up to 2 GHz. It's positioned against ARM’s Cortex A35/A55. The application domain of this class ranges from embedded systems, motor-control, IoT, storage, industrial applications to low-cost high-performance Linux based applications such as networking, gateways etc.

C-arty100T is a SoC build around C-class. The C-arty100T SoC is a single-chip 64-bit C-class microcontroller with 128MB DDR3 RAM, 16 General Purpose Input Output (GPIO) pins, a Platform Level Interrupt Controller (PLIC), a Counter, 1 Universal Asynchronous Receiver Transmitter (UART) and 1 Inter-Integrated Circuit (I2C). It is aimed at mid-range application workloads with a very low power consumption and has support for optional memory protection.

I-class
The I-class is a 64-bit processor which targets the compute, mobile, storage and networking platforms. Its features include out-of-order execution, multithreading, aggressive branch prediction, non-blocking caches and deep pipeline stages. The operational clock frequency of this processor is 1.5-2.5 GHz. The team is currently working on implementing atomics, Memory dependence prediction, Instruction Window/Scheduler optimizations, Implementation of some functional units, Performance analysis/projections, Optimizations to meet first-cut target frequency on 1 Ghz on 22nm processor.

M-class
A mobile class processor with a maximum of 8 cores, the cores being a combination of C and I class cores. The M-class processors are aimed at general-purpose compute, low-end server and mobile applications. The operation frequency ranges up to 2.5 GHz. Its supports large issue size, quad-threaded & optional NoC fabric. The M-class processors are optimised for various power and performance targets.

S-class
The S-Class is a 64-bit superscalar,multi-threaded variant aimed at Desktop and Enterprise server Application. Its supports 2-16 cores with a clock frequency of about 1.2-3 GHz.

H-class
The H-class is a 64-bit processor aimed at highly parallel enterprise, HPC and analytics applications. The cores can be a combination of C or I class, single-thread performance driving the core choice. The H-class has up to 128 cores with multiple accelerators per core.

Experimental Processors
These are experimental/research projects which focus on developing a high security and fault tolerent processor.

T-class
The T-class is aimed to provide additional hardware support for securing information from memory-based attacks. Its design focus on a unified hardware framework for mitigating spatial and temporal memory attacks.

F-class
The F-class is a fault-tolerant version of the base class processor. Features include redundant compute blocks (like DMR and TMR), temporal redundancy modules to detect permanent faults, lock-step core configurations, fault localization circuits, ECC for critical memory blocks and redundant bus fabrics.

Tapeouts
Two tapeouts of the C-class processors have been performed. They have been codenamed as RIMO and Rise-creek.

RIMO
RIMO is the code name of the SHAKTI C-class based SoC that has been tapeout at Semiconductor Laboratory (SCL) Indian Space Research Organizations (ISRO) at Chandigarh using 180 nm process technology. The 144 sq.mm. chip has been tested to operate at a frequency of up to 70 MHz. The chip has been packaged on a 208-pin Ceramic Quad Flat Pack (CQFP).

Risecreek
CREEK is the code name of the SHAKTI C-class based SoC that has been taped-out at INTEL, Oregon, the USA using 22 nm process technology. The 16 sq.mm. chip has been tested to operate at a frequency of up to 350 MHz. The chip has been packaged on a 208-pin Ball Grid Array (BGA)

Features of RIMO and Risecreek:
Some of the features of RIMO and Risecreek are as follows:


 * In-order 5 stage 64-bit microcontroller supporting the entire stable RISC-V ISA(RV64IMAFD).
 * Compatible with privilege spec (v1.10) of RISC-V ISA and supports the sv39 virtualisation scheme.
 * Includes a branch predictor with a Return-Address-Stack.
 * Pipelined IEEE-754 compliant single and double-precision floating point units and Multi-channel Direct Memory Access (DMA) support.
 * Peripherals like 2 x I2C, 2 x UART, 2 x QSPI, a Debugger, a 256KB tightly coupled memory, 32-bit GPIOs and an expansion bus that can be connected to an FPGA.

Development boards
There are development boards for both E and C class of processors. The details on the board support for different classes of processors are given below.

E-arty35T

 * E-arty35Tis a SoC based on SHAKTI E class [14].
 * E-arty35Tis supported on Artix 7 35T board.
 * It has an abridged version of 32 bit E class. It includes I, M, A and C.

C-arty100T

 * C-arty100Tis a SoC based on SHAKTI C class.
 * C-arty100Tis supported on Artix 7 100T board.
 * It has an abridged version of 64 bit C class. It includes I, M, A, F, D and C.