User:Su-steve/RCRelatedWork

Reconfigurable/polymorphic architectures

 * CMU PipeRench - Pipelineable FPGA, sort of (1997-2000).
 * MIT RAW - multiple processor tiles connected by a reconfigurable fabric (1997-2004).
 * Texas TRIPS - Multiple tiles connected via a network. Each tile has two processors, sixteen ALU's, L1 and L2 caches (2001-2006).

Architecture projects

 * Berkeley IRAM - Processor plus DRAM on the same chip.
 * Stanford FAST - FPGA prototype board for e.g. Hydra, below (2003-2006).
 * Stanford FLASH Multiprocessor - Multiple processor boards on a backplane. Each board includes a processor, DRAM, L2 cache, and configurable interconnect (1992-1997).
 * Stanford Hydra - Four-processor CMP with support for TLS (1994-2005).
 * Stanford Imagine
 * Wisconsin MultiScalar - Origins of speculative multithreading, similar to TLS. Uses multiple functional units to attack different segments of the out-of-order window in parallel. 1995-2001.

References that I'm not sure what to do with yet
http://www.cryptomath.com/~doug/2007-eos/cpu-fpga.pdf NTU students propose(?) a rather generic sort of CPU/FPGA hybrid. Apparently this was part of a course in Embedded Operating Systems and Architecture, taught in Fall 2007, taught by Chen-Mou Cheng (http://www.cryptomath.com/~doug/) at National Taiwan University (http://www.cryptomath.com/~doug/2007-eos/slides-1.pdf.

Related pages

 * User:Su-steve/Sandbox
 * User:Su-steve/SmartMemReduxPaper
 * Reconfigurable_computing