User:Swapnali akhade/sandbox

INTRODUCTION:
Direct Memory access is a method by which a peripheral device can control the processor's memory bus directly and transfers data directly to and from memory without passing it through CPU.with DMA we can transfer data to and from devices quickly. To manage data transfer and access the system bus,DMA requires numbers of hardware.However DMA are useful when the transfer rate exceeds anything possible with software.A short code which contain read from a port, store to memory, increment pointers, decrement a loop counter and then repeat according to counter value takes quite a few clock cycles per byte copied which a DMA contoller can do with no wasted cycles.

WORKING:
1.When any peripheral is sending data, notification is sent to DMA controller. 2.Then DMA controller sends DMA request to the CPU, asking permission to use the bus. 3.CPU first completes the current process, enters into supervisor mode 4.Then sends DMA acknowledge signal to the DMA controller, making bus available to the controller. 5.Now DMA controller itself reads and writes memory bytes, driving the address, data, and control     signal. When DMA controller is having control of bus, CPU’s address, data and control outputs are tristated. DMA transfers the data from source to destination address. 6.When data transfer is complete, DMA controller sends request. CPU then regains the control of bus and enters into user mode.

Every DMA transfer starts with the software programming the DMA controller, the device (either on-board a integration CPU chip or a discrete component) that manages these transactions. The code generally contains source and destination pointers, a counter,numerous bits that defines DMA mode and type. These may include source or destination type (I/O or memory), action to take on completion of the transaction (generate an interrupt, restart the controller, etc.), wait states for each CPU cycle, etc. DMA controller waits for some action to start the transfer. Perhaps an external I/O device signals it is ready by toggling a bit. Sometimes the software simply sets a "start now" flag. Regardless, the controller takes over the bus and starts making transfers. Each DMA transfer looks just like a pair of normal CPU cycles. A memory or I/O read from the DMA source address is followed by a corresponding write to the destination. The source and destination devices cannot tell if the CPU is doing the accesses or if the DMA controller is doing them.During each transfer DMA is not doing any computation and waiting for access to the bus. DMA has control until it chooses to release the bus back to the CPU.Once the entire transfer is complete the DMA controller may quietly go to sleep, or it may restart the transfer when the I/O is ready for another block, or it may signal the processor that the action is complete. The controller interrupts the CPU so the firmware can take the appropriate action.

SYNCHRONOUS DMA:
It moves a byte or word at a time between system memory and a peripheral, handshaking with the I/O port for each transfer. This sort of transfer recognizes that the port may not always be in a ready condition; the handshaking is a hardware mechanism to throttle the transactions. With this sort of transfer, the program sets up the controller and then carries on, oblivious to the state of the DMA transaction. The hardware moves one byte or word between memory and I/O each time the I/O port signals it is ready for another transaction. On each read indication, the DMA controller asserts Bus Request, waits for a Bus Acknowledge in response, and then takes over the bus for a single cycle. Then, the DMA controller goes idle again, waiting for another ready signal from the port. Thus, the program and DMA cycles share bus cycles, with the controller winning any contest for control of the bus. Sometimes this is called "Cycle Stealing".

BURST MODE DMA:
in contrast, generally assumes that the destination and source addresses can transfers with the same speed the controller can generate them. The program sets up the controller, and the entire source block is copied to the destination. The DMA controller gains exclusive access to the bus for the duration of the transfer, during which time the program is effectively shut down. Burst mode DMA can transfer data very rapidly indeed.

FLYBY DMA:
something this is not supported on many controllers, is a beast of a different color. The DMA controller gains access to the bus and puts the source or destination address out. Then, it initiates what is in effect a read and a write cycle simultaneously. The data is read from the source address, and written to the destination, at the same time. This implies that either the source or destination does not require an address, since it is very unlikely that both would use the same. For example copying data from memory to a FIFO port - the source address (a pointer to memory) increments on each transfer, while the destination is always the same FIFO. Flyby transactions are very fast since the read/write cycle pair is reduced to a single cycle. Both burst and synchronous types of transfers can be supported

MODES OF OPERATION:
DMA operations can be performed in either burst or single-cycle mode. Some DMA controllers support both.

BURST MODE:
In burst mode, the DMA controller keeps control of the bus until all the data buffered by the requesting device has been transferred to memory.

SINGLE CYCLE MODE:
In single-cycle mode, the DMA controller gives up the bus after each transfer. This minimizes the amount of time that the DMA controller keeps the processor off of the memory bus, but it requires that the bus request/acknowledge sequence be performed for every transfer. This overhead can result in a drop in overall system throughput if a lot of data needs to be transferred.

In most designs, we would use single cycle mode if the system cannot tolerate more than a few cycles of added interrupt latency. Likewise, if the peripheral devices can buffer very large amounts of data, causing the DMA controller to tie up the bus for an excessive amount of time, single-cycle mode is preferable. some DMA controllers have larger address registers than length registers. For instance, a DMA controller with a 32-bit address register and a 16-bit length register can access a 4GB memory space, but can only transfer 64KB per block. If application requires DMA transfers of larger amounts of data, software intervention is required after each block. Get on the bus: The simplest way to use DMA is to select a processor with an internal DMA controller. This eliminates the need for external bus buffers and ensures that the timing is handled correctly. Also, an internal DMA controller can transfer data to on-chip memory and peripherals, which is something that an external DMA controller cannot do. Because the handshake is handled on-chip, the overhead of entering and exiting DMA mode is often much faster than when an external controller is used. If an external DMA controller or processor is used, hardware must handle the transition between transfers correctly. To avoid the problem of bus contention, bus requests are inhibited if the bus is not free. This prevents the DMA controller from requesting the bus before the processor has reacquired it after a transfer.

DMA Controller: The DMA controller megafunction is designed for data transfer in different system environments. Two module types—type 0 and type 1—are provided, and the user can choose the number of each module type. Type 0 modules are designed to transfer data residing on the same bus, and Type 1 modules are designed to transfer data between two different buses. Each module can support up to 4 DMA channels; the megafunction supports up to 16 total DMA channels. Each DMA channel can be programmed for various features, such as transfer size, synchronized and unsynchronized transfer control, transfer priority, interrupt generation, memory and I/O address space, and address change direction. This megafunction is designed to work with 32-bit and 64-bit bus systems, including the PCI bus, PowerPC bus, and other CPU host buses. It can also be integrated with other megafunctions to form a complete functional block. This megafunction is available in Altera Hardware Description Language (AHDL), Verilog HDL, VHDL, and netlist format.

ADVANTAGES:
More efficient use of interrupts, increases data throughput, reduces hardware cost by eliminating the need for peripheral specific FIFO buffers.

USES:
floppy and hard disk controllers often use DMA to transfer data to and from the drive. This is a perfect application. The software arms the controller and then carries on. The hardware waits for the drive to get to the correct position and then performs the transfer without further reliance on the system software