User:Will.pugsley

If you have any hints and tips please let me know....

Transmission line pulse (TLP) is a way to study integrated circuit technologies and circuit behavior in the current and time domain of electrostatic discharge (ESD) events. The method was first proposed by Maloney and Khurana to meet a shortcoming of traditional ESD tests such as the such as Human body model(HBM), Machine Model(MM) and Charged Device Model(CDM) tests which merely tell you whether a circuit is ESD tolerant or not, but fail to reveal any information as to why a circuit is ESD strong or weak. The TLP test is designed to show you how the circuit behaves under ESD like conditions by applying similar stresses to an integrated circuit as compared to traditional ESD tests but doing this in such a way that device operation under ESD conditions can be further understood.

Shortcomeings of the HBM test.
The HBM test discharges a 100pF capacitor through a 1500 Ohm resistor and a device under test (DUT). The voltage and current stress applied to the DUT is short (~100ns) and constantly variable which makes it difficult to accriately determine the DUT's current/votlage profile under ESD stresses. The current/votlage profile can be used to further understnad device operation un der ESD conditions and diagnose weak circuits.

Advantages of the TLP test.
In contract to the HBM test the TLP tester is designed to apply a constant stress for a short period of time, mimiking the HBM stress levels and duration whilst allowing the current and votlage profile to be accriately measured. The votlage and current can be accriately measured because, as the applied stress is constant, the votlage and current can be averaged over the duration of the whole TLP test.

Basic principle of the TLP tester.
The most basic TLP is comprised of a 50 Ohm cable

Typically, before the capacitor is discharged, it is charged to voltages in the range 100V to 8000V. Typically, for [integrated circuits]], the voltage across the DUT will not exceed 20V during the discharge. which, where the initial voltage of the capacitor is much greater than the breakdown votlage of the integrated circuit, a current is forced through the integrated circuit. The approximate shape of the HBM current waveform is shown in figure 1??/ replicate real life ESD events as accurately as possible and provide a common standard so that different protection circuits can be compared. Initially, HBM tests are normally carried out at low energy levels and the test energy is increased until the device no longer meets the published chip specification, at which point the chip is deemed to have failed the test. The ESD rating of the chip is based on the highest HBM test voltage that the chip can withstand and still meet the published specifications. Therefore the HBM test tells you how immune a circuit is to ESD events but it does not provide any information on the internal operation of the circuit under ESD conditions.

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