User talk:94.25.170.78

NOTE: ^6 is my shorthand for upper bit set in table below. Bit twiddling formula is my conversion from entry value to associativity value unoptimized. Associativity is now documented being in the top 4 bits of each 16 bit halfword in EAX and EBX, and the top 4 bits of the low halfword of ECX and EDX. A value of 6 means 8 way - see below. Recently a value of 7 has been added to say use cpuid eax 4 ecx 2 results instead. See latest Intel ISA Prog Ref v42: or. Check cache info in /proc/cpuinfo if your system supports that, and/or install, or download and build, Todd Allen's cpuid package, and run the utility: it writes a paper about your cpu with one line per bit of info almost; Todd and I have exchanged info about AMD and Intel cpuid doc updates; and I track Linux-next cpuid and cpuinfo updates to keep Cygwin in sync, as well as being Cygwin cpuid package maintainer. /* fn        ^6  L2 cache and TLB					*/ /* * L2/L3 4 bit associativity	(1 << (a >> 1)) + (a & 1)*((1 << (a >> 1)) >> 1) * 0 cache or TLB disabled 0	 0	       1	0	      0	       1 -> 0 * 1 direct mapped	  1	  0	       1	0	      0	       1 * 2  2-way		  10	  1	      10	0	      1	      10 * 4  4-way		 100	 10	     100	0	     10	     100 * 6  8-way		 110	 11	    1000	0	    100	    1000 * 7 use 0x00000004/2 * 8 16-way		1000	100	   10000	0	   1000	   10000 * A 32-way		1010	101	  100000	0	  10000	  100000 * B 48-way		1011	101	  100000	1	  10000	  110000 * C 64-way		1100	110	 1000000	0	 100000	 1000000 * D 96-way		1101	110	 1000000	1	 100000	 1100000 * E 128-way		1110	111	10000000	0	1000000	10000000 * F fully associative	1111	111	10000000	1	1000000	11000000 -> 255 */ /*	     Fn xfn  Reg Off Len  Name			Description	*/ { 0x80000006, 0, EAX,  0, 12, "l2itlb2ment" },	// l2 i TLB 2 MB page entries. { 0x80000006, 0, EAX, 12,  4, "l2itlb2massoc" },	// l2 i TLB 2 MB page assoc. See table. { 0x80000006, 0, EAX, 16, 12, "l2dtlb2ment" },	// l2 d TLB 2 MB page entries. { 0x80000006, 0, EAX, 28,  4, "l2dtlb2massoc" },	// l2 d TLB 2 MB page assoc. See table. /*	     Fn xfn  Reg Off Len  Name			Description	*/ { 0x80000006, 0, EBX,  0, 12, "l2itlb4kent" },	// l2 i TLB 4 kB page entries. { 0x80000006, 0, EBX, 12,  4, "l2itlb4kassoc" },	// l2 i TLB 4 kB page assoc. See table. { 0x80000006, 0, EBX, 16, 12, "l2dtlb4kent" },	// l2 d TLB 4 kB page entries. { 0x80000006, 0, EBX, 28,  4, "l2dtlb4kassoc" },	// l2 d TLB 4 kB page assoc. See table. /*	     Fn xfn  Reg Off Len  Name			Description	*/ { 0x80000006, 0, ECX,  0,  8, "l2chelnbytes" },	// l2 cache line size bytes. { 0x80000006, 0, ECX,  8,  4, "l2cheln/tag" },	// l2 cache lines/tag. { 0x80000006, 0, ECX, 12,  4, "l2cheassoc" },	// l2 cache assoc. See table. { 0x80000006, 0, ECX, 16, 16, "l2chekb" },		// l2 cache kB. /*	      Fn xfn  Reg Off Len  Name			Description	*/ { 0x80000006, 0, EDX,  0,  8, "l3chelnbytes" },	// l3 cache line size bytes. { 0x80000006, 0, EDX,  8,  4, "l3cheln/tag" },	// l3 cache lines/tag. { 0x80000006, 0, EDX, 12,  4, "l3cheassoc" },	// l3 cache assoc. See table. { 0x80000006, 0, EDX, 16,  2, "[^6:d:16:17]" }, { 0x80000006, 0, EDX, 18, 14, "l3chemb/2" },	// l3 cache 512kB. 24.64.172.44 (talk) 04:50, 8 January 2021 (UTC) Brian Inglis