User talk:Harshit nigam

Simple set-reset latches [edit] SR NOR latch SR latch Illustration of SR latch operation. Red and black mean logical '1' and '0', respectively.

When using static gates as building blocks, the most fundamental latch is the simple SR latch, where S and R stand for set and reset. It can be constructed from a pair of cross-coupled NOR (Not OR) logic gates. The stored bit is present on the output marked Q.

Normally, in storage mode, the S and R inputs are both low, and feedback maintains the Q and Q outputs in a constant state, with Q the complement of Q. If S (Set) is pulsed high while R (Reset) is held low, then the Q output is forced high, and stays high when S returns to low; similarly, if R is pulsed high while S is held low, then the Q output is forced low, and stays low when R returns to low. SR latch operation S 	R 	Action 0 	0 	Keep state 0 	1 	Q = 0 1 	0 	Q = 1 1 	1 	Restricted combination The symbol for an SR latch.

The R = S = 1 combination is called a restricted combination because, as both NOR gates then output zeros, it breaks the logical equation Q = not Q. The combination is also inappropriate in circuits where both inputs may go low simultaneously (i.e. a transition from restricted to keep). The output would lock at either 1 or 0 depending on the propagation time relations between the gates (a race condition). In certain implementations, it could also lead to longer ringings (damped oscillations) before the output settles, and thereby result in undetermined values (errors) in high-frequency digital circuits. This condition is therefore usually avoided.

To overcome the restricted combination, one can add gates to the inputs that would convert (S,R) = (1,1) to one of the non-restricted combinations. That can be:

* Q = 1 (1,0) — referred to as an S-latch * Q = 0 (0,1) — referred to as an R-latch * Keep state (0,0) — referred to as an E-latch

Alternatively, the restricted combination can be made to toggle the output. The result is the JK latch.

Characteristic: Q+ = R'Q + R'S or Q+ = R'Q + S[1] [edit] SR NAND latch SR latch

This is an alternate model of the simple SR latch built with NAND (Not AND) logic gates. Set and reset now become active low signals, denoted S and R respectively. Otherwise, operation is identical to that of the SR latch. Historically, SR-latches have been predominant despite the notational inconvenience of active-low inputs. This is because NAND gates are cheaper to produce than NOR gates in the diode-transistor logic (DTL) and transistor-transistor logic (TTL) families, which were the basis of early integrated circuits before the complementary metal–oxide semiconductor (CMOS) family attained widespread use. Since the 1970s and still as of 2009[update], most integrated circuits are built using CMOS technology, where NAND gates are also preferred. SR latch operation S 	R 	Action 0 	0 	Restricted combination 0 	1 	Q = 1 1 	0 	Q = 0 1 	1 	Keep state Symbol for an SR NAND latch [edit] JK latch

The JK latch is much less used than the JK Flip-flop. The JK latch follows the following state table: JK Latch truth table J 	K 	Qnext 	Comment 0 	0 	Qprev 	No change 0 	1 	0 	Reset 1 	0 	1 	Set 1 	1 	Qprev 	Toggle

Hence, the JK latch is identical to an SR latch that is made to toggle its output when passed the restricted combination. [edit] Gated latches and conditional transparency

Latches are designed to be transparent. That is, input signal changes cause immediate changes in output.[nb 1] Alternatively, additional logic can be added to a simple transparent latch to make it non-transparent or opaque when another input (e.g., an "enable" input) is not asserted. By following a transparent-high latch with a transparent-low (or opaque-high) latch, a simple edge-triggered flip-flop can be implemented.[citation needed] [edit] Gated SR latch A gated SR latch circuit diagram constructed from NOR gates.

A synchronous SR latch (sometimes clocked SR flip-flop) can be made by adding a second level of NAND gates to the inverted SR latch (or a second level of NOR gates to the direct SR latch). The extra gates further invert the inputs so the simple SR latch becomes a gated SR latch (and a simple SR latch would transform into a gated SR latch with inverted enable).

With E high (enable true), the signals can pass through the input gates to the encapsulated latch; all signal combinations except for (0,0) = hold then immediately reproduce on the (Q,Q) output, i.e. the latch is transparent.

With E low (enable false) the latch is closed (opaque) and remains in the state it was left the last time E was high.

The enable input is sometimes a clock signal, but more often a read or write strobe. Gated SR latch operation E/C 	Action 0 	No action (keep state) 1 	The same as non-clocked SR latch symbol for a gated SR latch [edit] Gated D-latch Schematic diagram A D-type transparent latch D 	Input E 	Enable/clock Q 	Output Q 	Inverse of Q A gated D latch based on SR (NOR) latch

This latch is closely related to the gated SR latch and can be similarly constructed. It is also known as transparent latch, data latch, or simply gated latch. It has a data input and an enable signal (sometimes named clock, or control). The word transparent comes from the fact that, when the enable input is on, the signal propagates directly through the circuit, from the input D to the output Q.

Transparent latches are typically used as I/O ports or in asynchronous systems.[nb 2] They are available as integrated circuits, usually with multiple latches per circuit. For example, 74HC75 is a quadruple transparent latch in the ubiquitous 7400 series. D-latch truth table E/C 	D 		Q 	Q 	Comment 0 	X 	Qprev 	Qprev 	No change 1 	0 	0 	1 	Reset 1 	1 	1 	0 	Set Symbol for a gated D latch

The truth table shows that when the enable/clock input is 0, the D input has no effect on the output. When E/C is high, the output equals D. [edit] Gated T-Latch

This is another synchronous SR latch that toggles the previous output. If the toggle (T) input is high, the T latch (well known as T flip-flop) changes state ("toggles") whenever the clock input is strobed. If the T input is low, it holds the previous value. Characteristic equation is; Qnext = T ⊕ Qpre, where Qnext is the next state and Qprev is the previous state. T 	Qprev 	Qnext 	Comment 0 	0 	0 	Hold state 0 	1 	1 1 	0 	1 	Toggle state 1 	1 	0

A T flip-flop can also be built using a JK flip-flop (i.e., with T implemented by connecting J & K pins together) or D flip-flop (T input and Qprevious is connected to the D input through an XOR gate).