User talk:Pkmr56


 * 1)  Memory Management Unit 
 * 2) Memory Management
 * 3) • Contiguous Memory Allocation
 * 4) • Paged Memory Management
 * 5) • Virtual Memory
 * 6) Binding of Instructions and Data to Memory
 * 7) • Compile time:
 * 8) – known memory location
 * 9) – absolute code can be generated
 * 10) – must recompile code if starting location changes.
 * 11) • Load time:
 * 12) – generate relocatable code if memory location is
 * 13) not known at compile time.
 * 14) • Execution time:
 * 15) – process can be moved during its execution from
 * 16) one memory segment to another.
 * 17) –	need hardware support for address mapping
 * 18) Logical vs. Physical Address Space
 * 19) • A logical address space that is bound to a
 * 20) separate physical address space
 * 21) – Logical address – generated by the CPU;
 * 22) also referred to as virtual address.
 * 23) – Physical address – address generated by
 * 24) the memory management unit.
 * 25) • Logical and physical addresses are the same
 * 26) in compile-time and load-time addressbinding
 * 27) schemes.
 * 28) • Logical (virtual) and physical addresses differ
 * 29) in execution-time address-binding scheme.
 * 30) ECE 344 Operating Systems 6
 * 31) Memory-Management Unit (MMU)
 * 32) • Hardware device that maps logical/virtual to
 * 33) physical address.
 * 34) • In MMU the value in the relocation register is
 * 35) added to every address generated by a
 * 36) program at the time the address is sent to
 * 37) memory.
 * 38) • The program deals with logical addresses; it
 * 39) never sees the real physical addresses.
 * 40) Dynamic relocation/binding using a
 * 41) relocation register
 * 42) Memory Allocation
 * 43) Contiguous Memory Allocation
 * 44) • Multiple partitions for multiple processes
 * 45) • Relocation register and limit registers to protect
 * 46) processes from one another (and protect OS code)
 * 47) • Both registers are part of process context (i.e., PCB)
 * 48) • Relocation register contains value of smallest
 * 49) physical address
 * 50) • Limit register contains range of logical addresses
 * 51) • Each logical address must be less than the limit
 * 52) register.
 * 53) Hardware Support for Relocation
 * 54) and Limit Registers
 * 55)                      Operating Systems
 * 56) Multi-partition Allocation
 * 57) • Holes are blocks of available memory
 * 58) • Holes of various size are scattered
 * 59) throughout memory.
 * 60) • When a process arrives, it is allocated
 * 61) memory from a hole large enough to
 * 62) accommodate it.
 * 63) • Operating system maintains information
 * 64) about:
 * 65) –	allocated partitions
 * 66) –	free partitions (i.e., holes)
 * 67) Dynamic Storage Allocation Problem
 * 68) • How to satisfy a request for memory of size n
 * 69) from a list of free holes?
 * 70) • First-fit: Allocate the first hole that is big
 * 71) enough.
 * 72) • Best-fit: Allocate the smallest hole that is big
 * 73) enough; must search entire list, unless ordered
 * 74) by size. Produces the smallest leftover hole.
 * 75) • Worst-fit: Allocate the largest hole; must also
 * 76) search entire list. Produces the largest
 * 77) leftover hole
 * 78) Fragmentation
 * 79) • External Fragmentation – total memory space
 * 80) exists to satisfy a request, but it is not contiguous.
 * 81) • Internal Fragmentation – allocated memory may
 * 82) be slightly larger than requested memory; this size
 * 83) difference is memory internal to a partition, but not
 * 84) being used.
 * 85) • Reduce external fragmentation by compaction
 * 86) – Shuffle memory contents to place all free memory
 * 87) together in one large block.
 * 88) – Compaction is possible only if address binding is
 * 89) dynamic, and is done at execution time.
 * 90) Preview
 * 91) • The problem so far has been that we
 * 92) allocated memory in contiguous junks
 * 93) • What if we could allocate memory in noncontiguous
 * 94) junks?
 * 95) • We will be looking at techniques that aim at
 * 96) avoiding
 * 97) – External fragmentation
 * 98) –	(Internal fragmentation)
 * 99) Paging
 * 100) • Physical address space of a process can be noncontiguous;
 * 101) • Process is allocated physical memory whenever the latter is
 * 102) available.
 * 103) • Divide physical memory into fixed-sized blocks called
 * 104) frames (size is power of 2, between 512 bytes and 8192
 * 105) bytes, also larger sizes possible in practice.)
 * 106) • Divide logical memory into blocks of same size called
 * 107) pages.
 * 108) • Keep track of all free frames.
 * 109) • To run a program of size n pages, need to find n free
 * 110) frames and load program.
 * 111) • Set up a page table to translate logical to physical
 * 112) addresses.
 * 113) • Internal fragmentation, for last page
 * 114) Address Translation Scheme
 * 115) • Address generated by CPU is divided into:
 * 116) – Page number (p)
 * 117) • Used as an index into the page table
 * 118) • Page table contains base address of each page in
 * 119) physical memory.
 * 120) – Page offset (d)
 * 121) • combined with base address to define the
 * 122) physical memory address sent to the memory unit.
 * 123) Address Translation Architecture digram
 * 124) Paging Example:-
 * 125) Basic Implementation of a Page Table
 * 126) • Page table is kept in main memory.
 * 127) • Page-table base register (PTBR) points to the
 * 128) page table (part of process context).
 * 129) • Page-table length register (PRLR) indicates
 * 130) size of the page table (part of process context).
 * 131) Implementation of a Page Table
 * 132) • Every data and instruction access requires
 * 133) two memory accesses:
 * 134) – one for the page table and
 * 135) – one for the data or instruction.
 * 136) • A typical instruction has 1, 2, … operands,
 * 137) which all typically require memory access
 * 138) (through page table).
 * 139) • This is pretty inefficient, if done in software.
 * 140) • Mapping has to be fast.
 * 141) Implementation of a Page Table
 * 142) • 32 bit virtual address and 4k page size results
 * 143) in 1 million pages (232/212 = 220)
 * 144) • 4 byte page table entry, results in a 4MB table
 * 145) • Page table requires 1 million entries, each
 * 146) process has its own table
 * 147) • Page table can be extremely large.
 * 148) Implementation of a Page Table
 * 149) • Page table as a set of registers
 * 150) – Adds to context switch overhead
 * 151) – Page table usually too large
 * 152) • The two-memory access problem can be
 * 153) solved by the use of a special fast-lookup
 * 154) hardware cache called associative
 * 155) memory
 * 156) • A.k.a. a translation look-aside buffer (TLB)
 * 157) Page Table Structure
 * 158) • Addressing the page table size problem
 * 159) – Hierarchical Paging
 * 160) – Hashed Page Tables
 * 161) -Inverted Page Tables
 * 162) Hierarchical Page Tables
 * 163) • Allocating the page table contiguously in
 * 164) memory is not feasible
 * 165) • Break up the logical address space into
 * 166) multiple page tables
 * 167) • Recursively apply the paging scheme to the
 * 168) page table itself
 * 169) • A simple technique is a two-level page table
 * 170) Two-Level Paging Example
 * 171) • A logical address (on 32-bit machine with 4K page
 * 172) size) is divided into:
 * 173) – A page number consisting of 20 bits.
 * 174) – Possible address space of size 220 pages.
 * 175) – A page offset consisting of 12 bits.
 * 176) – 12 bits can address 4096 bytes (i.e., all bytes in the 4k
 * 177) page).
 * 178) • Since the page table is paged, the page number is
 * 179) further divided into:
 * 180) – a 10-bit page number.
 * 181) -a 10-bit page offset.
 * 182) Address-Translation Scheme
 * 183) • Address-translation scheme for a two-level
 * 184) 32-bit paging architecture
 * 185) Hashed Page Tables
 * 186) • Common in address spaces > 32 bits.
 * 187) • The virtual page number is hashed into a
 * 188) page table.
 * 189) • This page table contains a chain of elements
 * 190) hashing to the same location.
 * 191) • Virtual page numbers are compared in this
 * 192) chain searching for a match. If a match is
 * 193) found, the corresponding physical frame is
 * 194) extracted.
 * 195) Inverted Page Table
 * 196) • One entry for each real frame of memory.
 * 197) • Entry consists of the virtual address of the
 * 198) page stored in that real memory location, with
 * 199) information about the process that owns that
 * 200) page.
 * 201) • Decreases memory needed to store each
 * 202) page table, but increases time needed to
 * 203) search the table when a page reference
 * 204) occurs.
 * 205) • Use hash table to limit the search to one —
 * 206) or at most a few — page-table entries.
 * 207) Virtual Memory
 * 208) • Only part of the program needs to be in
 * 209) memory for execution.
 * 210) • Logical address space can therefore be
 * 211) much larger than physical address space.
 * 212) • Physical address spaces can be shared by
 * 213) several processes.
 * 214) • More efficient process creation.
 * 215) • Virtual memory can be implemented via
 * 216) – Demand paging
 * 217) –Demand segmentation
 * 218) Demand Paging
 * 219) • Bring a page into memory only when it is
 * 220) needed.
 * 221) – Less I/O needed
 * 222) – Less memory needed
 * 223) – Faster response
 * 224) – More users
 * 225) • Page is needed ⇒ reference to it
 * 226) – invalid reference ⇒ abort
 * 227) -not-in-memory ⇒ bring to memory
 * 228) Valid-Invalid Bit
 * 229) • With each page table entry a valid–
 * 230) invalid bit is associated
 * 231) (1 ⇒ in-memory, 0 ⇒ not-in-memory)
 * 232) • Initially valid–invalid bit is set to 0 on
 * 233) all entries
 * 234) • During address translation, if valid–
 * 235) invalid bit in page table entry is 0 ⇒
 * 236) page fault
 * 237) • Demand paging (all bits initially 0)
 * 238) What happens if there is no free frame?
 * 239) • Page replacement – find some page in
 * 240) memory, but not really in use, swap it out.
 * 241) – algorithm
 * 242) – performance
 * 243) • algorithm should result in minimum number of
 * 244) page faults
 * 245) • Same page may be brought into memory
 * 246) several times.
 * 247) Page Replacement
 * 248) • Prevent over-allocation of memory by
 * 249) modifying page-fault service routine to include
 * 250) page replacement
 * 251) • Use modify (dirty) bit to reduce overhead of
 * 252) page transfers
 * 253) – only modified pages need to be written to disk
 * 254) • Page replacement completes separation
 * 255) between logical memory and physical memory
 * 256) • Thus large virtual memory can be provided
 * 257) on a smaller physical memory
 * 258) Basic Page Replacement
 * 259) 􀂄 Find the location of the desired page on disk
 * 260) 􀂄 Find a free frame
 * 261) 􀂄 If there is a free frame, use it
 * 262) 􀂄 If there is no free frame, use a page
 * 263) replacement algorithm to select a victim frame
 * 264) 􀂄 Read the desired page into the (newly) freed
 * 265) frame
 * 266) 􀂄 Update the page table
 * 267) 􀂄 Restart the process
 * 268) Page replacement digram:-
 * 269) Page Replacement Algorithms
 * 270) • Want lowest page-fault rate.
 * 271) • Evaluate algorithm by running it on a
 * 272) particular string of memory references
 * 273) (reference string)
 * 274) • Compute the number of page faults on that
 * 275) string
 * 276) • In all our examples, the reference string is
 * 1, 2, 3, 4, 1, 2, 5, 1, 2, 3, 4, 5.
 * 1) Graph of Page Faults Versus The Number
 * 2) of Frames
 * 3) Fifo page replacement
 * 4) FIFO Illustrating Belady’s Anamoly (1976)
 * 5) Optimal Page Replacement
 * 6) Least Recently Used (LRU) Algorithm
 * 7) Reference string: 1, 2, 3, 4, 1, 2, 5, 1, 2, 3, 4, 5
 * 8) • use recent past as approximation
 * 9) of near future
 * 10) • Counter implementation
 * 11) – Every page table entry has a counter; every
 * 12) time page is referenced through this entry,
 * 13) copy the clock into the counter.
 * 14) – When a page needs to be replaced, look at
 * 15) the counters to determine least recently used
 * 16) LRU Page Replacement
 * 17) LRU Algorithm (Cont.)
 * 18) • Stack implementation – keep a stack of
 * 19) page numbers in a double link form
 * 20) • Page referenced
 * 21) • move it to the top
 * 22) • requires 6 pointers to be changed
 * 23) • No search for replacement
 * 24) Use Of A Stack to Record The Most Recent Page
 * 25) References
 * 26) LRU Approximation Algorithm 1
 * 27) • Reference bit
 * 28) –With each page associate a bit, initially all 0
 * 29) –When page is referenced bit set to 1
 * 30) – Replace the page which is 0 (if one exists)
 * 31) –We do not know the order, however
 * 32) LRU Approximation Algorithm 2
 * 33) • Keep several reference bits (e.g., 8 bits) per page
 * 34) • And keep the reference bit (as before)
 * 35) • At periodic intervals (timer interrupt, e.g., 100
 * 36) milliseconds) shift the reference bit of every page
 * 37) into the high-order position of the reference bit
 * 38) • Right shift the reference bits, dropping low order bit
 * 39) • 0000 0000 – not been used in past intervals
 * 40) • 1111 1111 – has been used each in interval
 * 41) • Interpret as unsigned integers, choose smallest as
 * 42) Victim
 * 43) LRU Approximation Algorithm 3
 * 44) • Second chance
 * 45) – Need 1 reference bit
 * 46) – Clock replacement
 * 47) – If page to be replaced (in clock order) has
 * 48) reference bit set to 1. then:
 * 49) • set reference bit 0.
 * 50) • leave page in memory.
 * 51) • replace next page (in clock order), subject to same
 * 52) rules.
 * 53) Second-Chance (clock) Page-Replacement
 * 54) Algorithm
 * 55) Counting Algorithms
 * 56) • Keep a counter of the number of references
 * 57) that have been made to each page
 * 58) • LFU Algorithm: replaces page with smallest
 * 59) count
 * 60) • MFU Algorithm: based on the argument that
 * 61) the page with the smallest count was
 * 62) probably just brought in and has yet to be
 * 63) used
 * 64) Allocation of Frames
 * 65) • Each process needs minimum number of
 * 66) pages
 * 67) • Example: IBM 370 – 6 pages to handle
 * 68) MOVE instruction:
 * 69) – instruction is 6 bytes, might span 2 pages
 * 70) – 2 pages to handle from
 * 71) –	2 pages to handle to
 * 72) Fixed Allocation
 * 73) • Two major allocation schemes
 * 74) – fixed allocation
 * 75) – priority allocation
 * 76) • Equal allocation – e.g., if 100 frames and 5
 * 77) processes, give each 20 pages.
 * 78) • Proportional allocation – Allocate according
 * 79) to the size of process.
 * 80) Priority Allocation
 * 81) • Use a proportional allocation scheme using
 * 82) priorities rather than size
 * 83) • If process Pi generates a page fault,
 * 84) – select for replacement one of its frames
 * 85) – select for replacement a frame from a process
 * 86) with lower priority number
 * 87) Global vs. Local Allocation
 * 88) • Global replacement – process selects a
 * 89) replacement frame from the set of all
 * 90) frames; one process can take a frame from
 * 91) another
 * 92) • Local replacement – each process selects
 * 93) from only its own set of allocated frames.
 * 94) Thrashing
 * 95) • If a process does not have “enough” pages, the
 * 96) page-fault rate is very high. This leads to:
 * 97) – low CPU utilization (ready queue is empty)
 * 98) – operating system (may) think that it needs to increase
 * 99) the degree of multiprogramming
 * 100) – another process added to the system
 * 101) – this process requires pages to be brought in …
 * 102) • Thrashing ≡ a process is busy swapping pages in
 * 103) and out (spends more time paging than executing.)
 * 104) Thrashing
 * 105) Locality
 * 106) • Why does paging work?
 * 107) • Due to locality (memory accesses are not random)
 * 108) • Locality model
 * 109) – Process migrates from one locality to another
 * 110) – Locality corresponds to a procedure call (local variables,
 * 111) some global variables and instructions of procedure)
 * 112) – Localities may overlap
 * 113) • Why does thrashing occur?
 * 114) sum over size of all localities >
 * 115) total physical memory size
 * 116) Working-Set Model (approximate locality)
 * 117) • Δ ≡ working-set window ≡ a fixed number of page
 * 118) references. Example: 10,000 instruction
 * 119) • WSSi (working set size of Process Pi) =
 * 120) total number of pages referenced in the most
 * 121) recent Δ (varies over time)
 * 122) – if Δ too small will not encompass entire locality.
 * 123) – if Δ too large will encompass several localities.
 * 124) – if Δ = ∞ ⇒ will encompass entire process.
 * 125) • D = Σ WSSi ≡ total frames demanded
 * 126) • if D > m ⇒ Thrashing (m is total physical memory)
 * 127) • Policy if D > m, then suspend one of the
 * 128) processes.
 * 129) Working-set model
 * 130) Keeping Track of the Working Set
 * 131) • Approximate with interval timer + a reference bit
 * 132) • Example: Δ = 10,000
 * 133) – Timer interrupts after every 5000 time units.
 * 134) – Keep in memory 2 bits for each page.
 * 135) – Whenever a timer interrupts copy reference bit to memory
 * 136) bits and sets the values of all reference bits to 0.
 * 137) – If one of the bits in memory = 1 ⇒ page in working set.
 * 138) • Why is this not completely accurate?
 * 139) • Improvement = 10 bits and interrupt every 1000
 * 140) time units (cost of interrupt!).
 * 141) Page-Fault Frequency Scheme
 * 142) Summary Memory Management
 * 143) • Contiguous memory management
 * 144) • Paging and segmentation
 * 145) • Virtual memory management based on
 * 146) demand paging
 * 147) • Page replacement algorithm
 * 148) • Frame allocation strategies
 * 149) • Thrashing
 * 150) • Locality and working set model
 * 151) Segmentation
 * 152) • Memory-management scheme that supports user’s
 * 153) view of memory.
 * 154) • A program is a collection of segments. A segment
 * 155) is a logical unit such as:
 * 156) main program,
 * 157) procedure,
 * 158) function,
 * 159) method,
 * 160) object,
 * 161) local variables, global variables,
 * 162) common block,
 * 163) stack,
 * 164) symbol table, arrays
 * 165) User’s View of a Program
 * 166) Segmentation Architecture
 * 167) • Logical address consists of a two tuple:
 * 168) ,
 * 169) • Segment table – maps two-dimensional
 * 170) physical addresses; each table entry has:
 * 171) – base – contains the starting physical address where
 * 172) the segments reside in memory.
 * 173) – limit – specifies the length of the segment.
 * 174) • Segment-table base register (STBR) points
 * 175) to the segment table’s location in memory.
 * 176) • Segment-table length register (STLR)
 * 177) indicates number of segments used by a
 * 178) program;
 * 179) Shared Pages
 * 180) • Shared code
 * 181) – One copy of read-only (reentrant) code
 * 182) shared among processes (i.e., text editors,
 * 183) compilers, window systems).
 * 184) – Shared code must appear in same location in
 * 185) the logical address space of all processes.
 * 186) • Private code and data
 * 187) – Each process keeps a separate copy of the
 * 188) code and data.
 * 189) – The pages for the private code and data can
 * 190) appear anywhere in the logical address
 * 191) space.
 * 1) • Memory-management scheme that supports user’s
 * 2) view of memory.
 * 3) • A program is a collection of segments. A segment
 * 4) is a logical unit such as:
 * 5) main program,
 * 6) procedure,
 * 7) function,
 * 8) method,
 * 9) object,
 * 10) local variables, global variables,
 * 11) common block,
 * 12) stack,
 * 13) symbol table, arrays
 * 14) User’s View of a Program
 * 15) Segmentation Architecture
 * 16) • Logical address consists of a two tuple:
 * 17) ,
 * 18) • Segment table – maps two-dimensional
 * 19) physical addresses; each table entry has:
 * 20) – base – contains the starting physical address where
 * 21) the segments reside in memory.
 * 22) – limit – specifies the length of the segment.
 * 23) • Segment-table base register (STBR) points
 * 24) to the segment table’s location in memory.
 * 25) • Segment-table length register (STLR)
 * 26) indicates number of segments used by a
 * 27) program;
 * 28) Shared Pages
 * 29) • Shared code
 * 30) – One copy of read-only (reentrant) code
 * 31) shared among processes (i.e., text editors,
 * 32) compilers, window systems).
 * 33) – Shared code must appear in same location in
 * 34) the logical address space of all processes.
 * 35) • Private code and data
 * 36) – Each process keeps a separate copy of the
 * 37) code and data.
 * 38) – The pages for the private code and data can
 * 39) appear anywhere in the logical address
 * 40) space.
 * 1) – Each process keeps a separate copy of the
 * 2) code and data.
 * 3) – The pages for the private code and data can
 * 4) appear anywhere in the logical address
 * 5) space.