User talk:Rajavel.rv

FATAL ERROR IN VHDL:

Occur in time period error:

It occur for time period during in sequential execution

• Data<=”0000”, “0001” after 100 ns, “0010” after 50 ns;

Rectification:

Because “after” was sequential execution statement if this error rectification by

• Data<=”0000”, “0001” after 100 ns, “0010” after 200 ns;

Otherwise we are using for wait statement it happening concurrent execution statement…..

• Data<=”0000”; wait for 100 ns; • Data<=”0001”; wait for 50 ns; • Data<=”0010”; wait for 200 ns;

Fatal errors occur in Simulation Process: Modelsim: Using delay for “ps” (Pico second) in coding but the simulation process given time period for “ns” (Nano second) so that error was occur.

Rectification: Simulate-> Runtime simulation: Given 100 ps in Default run…….

Otherwise given time period for Rectification: Simulate-> Simulate -> Start Simulation -> Given 100 ps in Resolution...