User talk:Sevenalso234432

Why are you railing on and on and on about OVM and UVM on a page about SystemVerilog? I would have thought that an engineer as smart as you purport to be would have the ability to distinguish between a page about a programming language and a page about a class library.

If you have ever worked on a verification project of any size, how could you possibly claim that it would take a day to convert a SystemVerilog environment to use C++?

And if that claim were true, how can it possibly be that SystemVerilog is feature-rich enough that it offers a sufficiently one-to-one correlation with C++? It isn't, and it doesn't, by the way - but you were the one who inadvertently made that claim.

Why do you think the test bench features of SystemVerilog are closer to Verilog than Java? Classes are more like Verilog than Java? Dynamic memory allocation has more to do with Verilog than Java? Inheritance has more to do with Verilog than Java? Polymorphism has more to do with Verilog than Java? Encapsulation has more to do with Verilog than Java? Data hiding has more to do with Verilog than Java? Generic programming and static polymorphism have more to do with Verilog than Java?

Do you think that maybe - just maybe - you inability to find work has less to do with "job discrimination" against engineers without SystemVerilog experience, and more to do with your personality and behaviour? And the fact that you make such easily refutable claims such as the ones debunked above? — Preceding unsigned comment added by 184.144.134.12 (talk) 01:10, 29 September 2011 (UTC)