User talk:Wangfengzhou001

为什么我存在，因为我要世界不一样，所以我必须不一样. 如何去写报告使用的格式：IEEE http://www.ieee.org/publications_standards/publications/authors/author_templates.html

southampton university ECS ELEC6016: Digital Systems Synthesis error 1: prog.hex 6C2101   // 24'b0110_1100_0010_0001_1111_1110   BNE  %1, %0, -2;  branch if %1!=0      --the hex code is wrong ;should be 6C21FE and this is still wrong since it pick wrong %1 rather than %0 084200   // 24'b0000_1000_0100_0010_0000_0000   ADD  %2, %2, %0;  %2 = %2, display reg 2 ---is not display %2 and it display %2+%2 084200   // 24'b0000_1000_0100_0010_0000_0000   ADD  %2, %2, %0;  %2 = %2, display reg 2

error 2: alu.sv flags = 3'b0; is not match with the defination and it should be flags =4'b0.this will not indentify by modelsim

error 3: / unconditional absolute branches // J addr; PC <= addr `define J   6b'010_000 this are two error :1 .it should be 6'bxxxxxx 2.In the formal code 6b'010000 should not be put on there as a way of commant

error 4: decodertest.sv //- code starts here - // instruction decoder always_comb begin // default output signal values PCincr = 1'b1; // PC increments by default ALUfunc = 3'b000; imm=0; w1=0; w2=0; case(opcode) `LDI : begin w1 = 1'b1; // dest register imm = 1'b1; // direct imm data to data_a end endcase // opcode

end // always_comb how can testbench can write in this way with case inside of it??????????????????????????????

warning : wire cannot be systhesised so never ever use it logic should be with signed or unsigned to make the code formal