Wikipedia:Cleanup Taskforce/Front side bus

Front Side Bus
The article asserts:

For example, the current Core 2 architecture seems to perform better at a 1:1 ratio (that is, FSB1066 - true 266 MHz * quad-pumping - and DDR2-533 - true 266 MHz * double pumping) than a 4:5 ratio (using DDR2-667), but stepping it up to a 2:3 ratio (DDR2-800) or higher seems to increase performance over a 1:1 ratio.

Although no justification or reference is provided.

All-in-all the FSB topic is very important and this article really needs to be rewritten by someone with a deep technical understanding of processors and chip sets, and practical experience in overclocking.

Is this the best title for the article? RJFJR 16:41, 19 October 2006 (UTC)
 * I checked and system bus redirects to it so it may be the best name for the article. RJFJR 15:14, 25 October 2006 (UTC)

What this needs to say is the relaytionship between the FSB and the rest of the system. I don't know technically but is the FSB the interface bus between the CPU aand  the  I/O controller and Memory  or is just be betwqeen the CPU and  Memory. Or just between the CPU and I/o. Knowing this then we can make decisions regarding Over clocking memory clocks speed and other decisions.

Closed RJFJR 03:33, 24 September 2007 (UTC)