Xilinx

Xilinx, Inc. was an American technology and semiconductor company that primarily supplied programmable logic devices. The company is known for inventing the first commercially viable field-programmable gate array (FPGA). It also created the first fabless manufacturing model.

Xilinx was co-founded by Ross Freeman, Bernard Vonderschmitt, and James V Barnett II in 1984. The company went public on the NASDAQ in 1990. AMD announced its acquisition of Xilinx in October 2020, and the deal was completed on February 14, 2022, through an all-stock transaction worth an estimated $60 billion. Xilinx remained a wholly owned subsidiary of AMD until the brand was phased out in June 2023, with Xilinx's product lines now branded under AMD.

Company overview
Xilinx was founded in Silicon Valley in 1984 and is headquartered in San Jose, United States, with additional offices in Longmont, United States; Dublin, Ireland; Singapore; Hyderabad, India; Beijing, China; Shanghai, China; Brisbane, Australia, Tokyo, Japan and Yerevan, Armenia.

According to Bill Carter, former CTO and current fellow at Xilinx, the choice of the name Xilinx refers to the chemical symbol for silicon Si. The "linx" represents programmable links that connect programmable logic blocks together. The 'X's at each end represent the programmable logic blocks.

Xilinx sells a broad range of FPGAs, complex programmable logic devices (CPLDs), design tools, intellectual property, and reference designs. Xilinx customers represent just over half of the entire programmable logic market, at 51%. Altera (now subsidiary of Intel) is Xilinx's strongest competitor with 34% of the market. Other key players in this market are Actel (now subsidiary of Microsemi) and Lattice Semiconductor.

Early history
Ross Freeman, Bernard Vonderschmitt, and James V Barnett II—all former employees of Zilog, an integrated circuit and solid-state device manufacturer—co-founded Xilinx in 1984 with headquarters in San Jose, USA.

While working for Zilog, Freeman wanted to create chips that acted like a blank tape, allowing users to program the technology themselves. "The concept required lots of transistors and, at that time, transistors were considered extremely precious—people thought that Ross's idea was pretty far out", said Xilinx Fellow Bill Carter, hired in 1984 to design ICs as Xilinx's eighth employee.

It was at the time more profitable to manufacture generic circuits in massive volumes than specialized circuits for specific markets. FPGAs promised to make specialized circuits profitable.

Freeman could not convince Zilog to invest in FPGAs to chase a market then estimated at $100 million, so he and Barnett left to team up with Vonderschmitt, a former colleague. Together, they raised $4.5 million in venture funding to design the first commercially viable FPGA. They incorporated the company in 1984 and began selling its first product by 1985.

By late 1987, the company had raised more than $18 million in venture capital (equivalent to $ million in ) and was making nearly $14 million a year.

Expansion
From 1988 to 1990, the company's revenue grew each year, from $30 million to $100 million. During this time, Monolithic Memories Inc. (MMI), the company which had been providing funding to Xilinx, was purchased by AMD. As a result, Xilinx dissolved the deal with MMI and went public on the NASDAQ in 1989. The company also moved to a 144000 sqft plant in San Jose, California, to handle increasingly large orders from HP, Apple Inc., IBM and Sun Microsystems.

Other FPGA makers emerged in the mid-1990s. By 1995, the company reached $550 million in revenue. Over the years, Xilinx expanded operations to India, Asia and Europe.

Xilinx's sales rose to $2.53 billion by the end of its fiscal year 2018. Moshe Gavrielov – an EDA and ASIC industry veteran who was appointed president and CEO in early 2008 – introduced targeted design platforms that combine FPGAs with software, IP cores, boards and kits to address focused target applications. These platforms provide an alternative to costly application-specific integrated circuits (ASICs) and application-specific standard products (ASSPs).

On January 4, 2018, Victor Peng, the company's COO, replaced Gavrielov as CEO.

Recent history
In 2011, the company introduced the Virtex-7 2000T, the first product based on 2.5D stacked silicon (based on silicon interposer technology) to deliver larger FPGAs than could be built using standard monolithic silicon. Xilinx then adapted the technology to combine formerly separate components in a single chip, first combining an FPGA with transceivers based on heterogeneous process technology to boost bandwidth capacity while using less power.

According to former Xilinx CEO Moshe Gavrielov, the addition of a heterogeneous communications device, combined with the introduction of new software tools and the Zynq-7000 line of 28 nm SoC devices that combine an ARM core with an FPGA, are part of shifting its position from a programmable logic device supplier to one delivering “all things programmable”.

In addition to Zynq-7000, Xilinx product lines include the Virtex, Kintex and Artix series, each including configurations and models optimized for different applications. In April 2012, the company introduced the Vivado Design Suite - a next-generation SoC-strength design environment for advanced electronic system designs. In May, 2014, the company shipped the first of the next generation FPGAs: the 20 nm UltraScale.

In September 2017, Amazon.com and Xilinx started a campaign for FPGA adoption. This campaign enables AWS Marketplace's Amazon Machine Images (AMIs) with associated Amazon FPGA Instances created by partners. The two companies released software development tools to simplify the creation of FPGA technology. The tools create and manage the machine images created and sold by partners.

In July 2018, Xilinx acquired DeepPhi Technology, a Chinese machine learning startup founded in 2016. In October 2018, the Xilinx Virtex UltraScale+ FPGAs and NGCodec's H.265 video encoder were used in a cloud-based video coding service using the High Efficiency Video Coding (HEVC). The combination enables video streaming with the same visual quality as that using GPUs, but at 35%-45% lower bitrate.

In November 2018, the company's Zynq UltraScale+ family of multiprocessor system-on-chips was certified to Safety Integrity Level (SIL) 3 HFT1 of the IEC 61508 specification. With this certification, developers are able to use the MPSoC platform in AI-based safety- applications of up to SIL 3, in industrial 4.0 platforms of automotive, aerospace, and AI systems. In January 2019, ZF Friedrichshafen AG (ZF) worked with Xilinx's Zynq to power its ProAI automotive control unit, which is used to enable automated driving applications. Xilinx's platform overlooks the aggregation, pre-processing, and distribution of real-time data, and accelerates the AI processing of the unit.

In November 2018, Xilinx migrated its defense-grade XQ UltraScale+ products to TSMC's 16 nm FinFET Process. The products included the industry's first Defense-grade heterogeneous multi-processor SoC devices and encompassed the XQ Zynq UltraScale+ MPSoCs and RFSoCs as well as XQ UltraScale+ Kintex and Virtex FPGAs. That same month the company expanded its Alveo data center accelerator cards portfolio with the Alveo U280. The initial Alveo line included the U200 and U250, which featured 16 nm UltraScale+ Virtex FPGAs and DDR4 SDRAM. Those two cards were launched in October 2018 at the Xilinx Developer Forum. At the Forum, Victor Peng, CEO of semiconductor design at Xilinx, and AMD CTO Mark Papermaster, used eight Alveo U250 cards and two AMD Epyc 7551 server CPUs to set a new world record for inference throughput at 30,000 images per second.

Also in November 2018, Xilinx announced that Dell EMC was the first server vendor to qualify its Alveo U200 accelerator card, used to accelerate key HPC and other workloads with select Dell EMC PowerEdge servers. The U280 included support for high-bandwidth memory (HBM2) and high-performance server interconnect. In August 2019, Xilinx launched the Alveo U50, a low-profile adaptable accelerator with PCIe Gen4 support. The U55C accelerator card was launched in November 2021, designed for HPCC and big data workloads by incorporating the RoCE v2-based clustering solution, allowing for FPGA-based HPCC clustering to be integrated into existing data center infrastructures.

In January 2019 K&L Gates, a law firm representing Xilinx sent a DMCA cease and desist letter to an EE YouTuber claiming trademark infringement for featuring the Xilinx logo next to Altera's in an educational video. Xilinx refused to reply until a video outlining the legal threat was published, after which they sent an apology e-mail.

In January 2019, Baidu announced that its new edge acceleration computing product, EdgeBoard, was powered by Xilinx. Edgeboard is a part of the Baidu Brain AI Hardware Platform Initiative, which encompasses Baidu's open computing services, and hardware and software products for its edge AI applications. Edgeboard is based on the Xilinx Zynq UltraScale+ MPSoC, which uses real-time processors together with programmable logic. The Xilinx-based Edgeboard can be used to develop products like smart-video security surveillance solutions, advanced-driver-assistance systems, and next-generation robots.

In February 2019, the company announced two new generations of its Zynq UltraScale+ RF system on chip (RFSoC) portfolio. The device covers the entire sub-6 GHz spectrum, which is necessary for 5G, and the updates included: an extended millimeter wave interface, up to 20% power reduction in the RF data converter subsystem compared to the base portfolio, and support of 5G New Radio. The second generation release covered up to 5 GHz, while the third went up to 6 GHz. As of February, the portfolio was the only adaptable radio platform single chip that had been designed to address the industry's 5G network needs. The second announcement revealed that Xilinx and Samsung Electronics performed the world's first 5G New Radio (NR) commercial deployment in South Korea. The two companies developed and deployed 5G Massive Multiple-input, Multiple-output (m-MIMO) and millimeter wave (mmWave) products using Xilinx's UltraScale+ platform. The capabilities are essential for 5G commercialization. The companies also announced collaboration on Xilinx's Versal adaptable compute acceleration platform (ACAP) products that will deliver 5G services. In February 2019, Xilinx introduced an HDMI 2.1 IP subsystem core, which enabled the company's devices to transmit, receive, and process up to 8K (7680 x 4320 pixels) UHD video in media players, cameras, monitors, LED walls, projectors, and kernel-based virtual machines.

In April 2019, Xilinx entered into a definitive agreement to acquire Solarflare Communications, Inc. Xilinx became a strategic investor in Solarflare in 2017. The companies have been collaborating since then on advanced networking technology, and in March 2019 demonstrated their first joint solution: a single-chip FPGA-based 100G NIC. The acquisition enables Xilinx to combine its FPGA, MPSoC and ACAP solutions with Solarflare's NIC technology. In August 2019, Xilinx announced that the company would be adding the world's largest FPGA - the Virtex Ultrascale+ VU19P, to the 16 nm Virtex Ultrascale+ family. The VU19P contains 35 billion transistors.

In June 2019, Xilinx announced that it was shipping its first Versal chips. Using ACAP, the chips’ hardware and software can be programmed to run almost any kind of AI software. On October 1, 2019, Xilinx announced the launch of Vitis, a unified free and open source software platform that helps developers take advantage of hardware adaptability.

In 2019, Xilinx exceeded $3 billion in annual revenues for the first time, announcing revenues of $3.06 billion, up 24% from the prior fiscal year. Revenues were $828 million for the fourth quarter of the fiscal year 2019, up 4% from the prior quarter and up 30% year over year. Xilinx's Communications sector represented 41% of the revenue; the industrial, aerospace and defense sectors represented 27%; the Data Center and Test, Measurement & Emulation (TME) sectors accounted for 18%; and the automotive, broadcast and consumer markets contributed 14%.

In August 2020, Subaru announced the use of one of Xilinx's chips as processing power for camera images in its driver-assistance system. In September 2020, Xilinx announced its new chipset, the T1 Telco Accelerator card, that can be used for units running on an open RAN 5G network.

On October 27, 2020, AMD reached an agreement to acquire Xilinx in a stock-swap deal, valuing the company at $35 billion. The deal was expected to close by the end of 2021. Their stockholders approved the acquisition on April 7, 2021. The deal was completed on February 14, 2022. Since the acquisition was completed, all Xilinx products are co-branded as AMD Xilinx; started in June 2023, all Xilinx's products are now being consolidated under AMD's branding.

In December 2020, Xilinx announced they were acquiring the assets of Falcon Computing Systems to enhance the free and open source Vitis platform, a design software for adaptable processing engines to enable highly optimized domain specific accelerators.

In April 2021, Xilinx announced a collaboration with Mavenir to boost cell phone tower capacity for open 5G networks. That same month, the company unveiled the Kria portfolio, a line of small form factor system-on-modules (SOMs) that come with a pre-built software stack to simplify development. In June, Xilinx announced it was acquiring German software developer Silexica, for an undisclosed amount.

Technology


Xilinx designs and develops programmable logic products, including integrated circuits (ICs), software design tools, predefined system functions delivered as intellectual property (IP) cores, design services, customer training, field engineering and technical support. Xilinx sells both FPGAs and CPLDs for electronic equipment manufacturers in end markets such as communications, industrial, consumer, automotive and data processing.

Xilinx's FPGAs have been used for the ALICE (A Large Ion Collider Experiment) at the CERN European laboratory on the French-Swiss border to map and disentangle the trajectories of thousands of subatomic particles. Xilinx has also engaged in a partnership with the United States Air Force Research Laboratory's Space Vehicles Directorate to develop FPGAs to withstand the damaging effects of radiation in space, which are 1,000 times less sensitive to space radiation than the commercial equivalent, for deployment in new satellites. Xilinx FPGAs can run a regular embedded OS (such as Linux or vxWorks) and can implement processor peripherals in programmable logic. The Virtex-II Pro, Virtex-4, Virtex-5, and Virtex-6 FPGA families, which include up to two embedded IBM PowerPC cores, are targeted to the needs of system-on-chip (SoC) designers.

Xilinx's IP cores include IP for simple functions (BCD encoders, counters, etc.), for domain specific cores (digital signal processing, FFT and FIR cores) to complex systems (multi-gigabit networking cores, the MicroBlaze soft microprocessor and the compact Picoblaze microcontroller). Xilinx also creates custom cores for a fee.

The main design toolkit Xilinx provides engineers is the Vivado Design Suite, an integrated design environment (IDE) with a system-to-IC level tools built on a shared scalable data model and a common debug environment. Vivado includes electronic system level (ESL) design tools for synthesizing and verifying C-based algorithmic IP; standards based packaging of both algorithmic and RTL IP for reuse; standards based IP stitching and systems integration of all types of system building blocks; and the verification of blocks and systems. A free version WebPACK Edition of Vivado provides designers with a limited version of the design environment.

Xilinx's Embedded Developer's Kit (EDK) supports the embedded PowerPC 405 and 440 cores (in Virtex-II Pro and some Virtex-4 and -5 chips) and the Microblaze core. Xilinx's System Generator for DSP implements DSP designs on Xilinx FPGAs. A freeware version of its EDA software called ISE WebPACK is used with some of its non-high-performance chips. Xilinx is the only (as of 2007) FPGA vendor to distribute a native Linux freeware synthesis toolchain.

Xilinx announced the architecture for a new ARM Cortex-A9-based platform for embedded systems designers, that combines the software programmability of an embedded processor with the hardware flexibility of an FPGA. The new architecture abstracts much of the hardware burden away from the embedded software developers' point of view, giving them an unprecedented level of control in the development process. With this platform, software developers can leverage their existing system code based on ARM technology and utilize vast off-the-shelf open-source and commercially available software component libraries. Because the system boots an OS at reset, software development can get under way quickly within familiar development and debug environments using tools such as ARM's RealView development suite and related third-party tools, Eclipse-based IDEs, GNU, the Xilinx Software Development Kit and others. In early 2011, Xilinx began shipping the Zynq-7000 SoC platform immerses ARM multi-cores, programmable logic fabric, DSP data paths, memories and I/O functions in a dense and configurable mesh of interconnect. The platform targets embedded designers working on market applications that require multi-functionality and real-time responsiveness, such as automotive driver assistance, intelligent video surveillance, industrial automation, aerospace and defense, and next-generation wireless.

Following the introduction of its 28 nm 7-series FPGAs, Xilinx revealed that several of the highest-density parts in those FPGA product lines will be constructed using multiple dies in one package, employing technology developed for 3D construction and stacked-die assemblies. The company's stacked silicon interconnect (SSI) technology stacks several (three or four) active FPGA dies side by side on a silicon interposer – a single piece of silicon that carries passive interconnect. The individual FPGA dies are conventional, and are flip-chip mounted by microbumps on to the interposer. The interposer provides direct interconnect between the FPGA dies, with no need for transceiver technologies such as high-speed SerDes. In October 2011, Xilinx shipped the first FPGA to use the new technology, the Virtex-7 2000T FPGA, which includes 6.8 billion transistors and 20 million ASIC gates. The following spring, Xilinx used 3D technology to ship the Virtex-7 HT, the industry's first heterogeneous FPGAs, which combine high bandwidth FPGAs with a maximum of sixteen 28 Gbit/s and seventy-two 13.1 Gbit/s transceivers to reduce power and size requirements for key Nx100G and 400G line card applications and functions.

In January 2011, Xilinx acquired design tool firm AutoESL Design Technologies and added System C high-level design for its 6- and 7-series FPGA families. The addition of AutoESL tools extended the design community for FPGAs to designers more accustomed to designing at a higher level of abstraction using C, C++ and System C.

In April 2012, Xilinx introduced a revised version of its toolset for programmable systems, called Vivado Design Suite. This IP and system-centric design software supports newer high capacity devices, and speeds the design of programmable logic and I/O. Vivado provides faster integration and implementation for programmable systems into devices with 3D stacked silicon interconnect technology, ARM processing systems, analog mixed signal (AMS), and many semiconductor intellectual property (IP) cores.

In July 2019, Xilinx acquired NGCodec, developers of FPGA accelerated video encoders for video streaming, cloud gaming and cloud mixed reality services. NGCodec video encoders include support for H.264/AVC, H.265/HEVC, VP9 and AV1, with planned future support for H.266/VVC and AV2.

In May 2020, Xilinx installed its first Adaptive Compute Cluster (XACC) at ETH Zurich in Switzerland. The XACCs provide infrastructure and funding to support research in adaptive compute acceleration for high performance computing (HPC). The clusters include high-end servers, Xilinx Alveo accelerator cards, and high speed networking. Three other XACCs will be installed at the University of California, Los Angeles (UCLA); the University of Illinois at Urbana Champaign (UIUC); and the National University of Singapore (NUS).

Family lines of products


Before 2010, Xilinx offered two main FPGA families: the high-performance Virtex series and the high-volume Spartan series, with a cheaper EasyPath option for ramping to volume production. The company also provides two CPLD lines: the CoolRunner and the 9500 series. Each model series has been released in multiple generations since its launch. With the introduction of its 28 nm FPGAs in June 2010, Xilinx replaced the high-volume Spartan family with the Kintex family and the low-cost Artix family.

Xilinx's newer FPGA products use a High-K Metal Gate (HKMG) process, which reduces static power consumption while increasing logic capacity. In 28 nm devices, static power accounts for much and sometimes most of the total power dissipation. Virtex-6 and Spartan-6 FPGA families are said to consume 50 percent less power, and have up to twice the logic capacity compared to the previous generation of Xilinx FPGAs.

In June 2010, Xilinx introduced the Xilinx 7 series: the Virtex-7, Kintex-7, and Artix-7 families, promising improvements in system power, performance, capacity, and price. These new FPGA families are manufactured using TSMC's 28 nm HKMG process. The 28 nm series 7 devices feature a 50 percent power reduction compared to the company's 40 nm devices and offer capacity of up to 2 million logic cells. Less than one year after announcing the 7 series 28 nm FPGAs, Xilinx shipped the world's first 28 nm FPGA device, the Kintex-7. In March 2011, Xilinx introduced the Zynq-7000 family, which integrates a complete ARM Cortex-A9 MPCore processor-based system on a 28 nm FPGA for system architects and embedded software developers. In May 2017, Xilinx expanded the 7 Series with the production of the Spartan-7 family.

In Dec, 2013, Xilinx introduced the UltraScale series: Virtex UltraScale and Kintex UltraScale families. These new FPGA families are manufactured by TSMC in its 20 nm planar process. At the same time it announced an UltraScale SoC architecture, called Zynq UltraScale+ MPSoC, in TSMC 16 nm FinFET process.

In March 2021, Xilinx announced a new cost-optimized portfolio with Artix and Zynq UltraScale+ devices, fabricated on TSMC's 16 nm process.

Virtex family
The Virtex series of FPGAs have integrated features that include FIFO and ECC logic, DSP blocks, PCI-Express controllers, Ethernet MAC blocks, and high-speed transceivers. In addition to FPGA logic, the Virtex series includes embedded fixed function hardware for commonly used functions such as multipliers, memories, serial transceivers and microprocessor cores. These capabilities are used in applications such as wired and wireless infrastructure equipment, advanced medical equipment, test and measurement, and defense systems.

The Virtex 7 family, is based on a 28 nm design and is reported to deliver a two-fold system performance improvement at 50 percent lower power compared to previous generation Virtex-6 devices. In addition, Virtex-7 doubles the memory bandwidth compared to previous generation Virtex FPGAs with 1866 Mbit/s memory interfacing performance and over two million logic cells.

In 2011, Xilinx began shipping sample quantities of the Virtex-7 2000T "3D FPGA", which combines four smaller FPGAs into a single package by placing them on a special silicon interconnection pad (called an interposer) to deliver 6.8 billion transistors in a single large chip. The interposer provides 10,000 data pathways between the individual FPGAs – roughly 10 to 100 times more than would usually be available on a board – to create a single FPGA. In 2012, using the same 3D technology, Xilinx introduced initial shipments of their Virtex-7 H580T FPGA, a heterogeneous device, so called because it comprises two FPGA dies and one 8-channel 28 Gbit/s transceiver die in the same package.

The Virtex-6 family is built on a 40 nm process for compute-intensive electronic systems, and the company claims it consumes 15 percent less power and has 15 percent improved performance over competing 40 nm FPGAs.

The Virtex-5 LX and the LXT are intended for logic-intensive applications, and the Virtex-5 SXT is for DSP applications. With the Virtex-5, Xilinx changed the logic fabric from four-input LUTs to six-input LUTs. With the increasing complexity of combinational logic functions required by SoC designs, the percentage of combinational paths requiring multiple four-input LUTs had become a performance and routing bottleneck. The six-input LUT represented a tradeoff between better handling of increasingly complex combinational functions, at the expense of a reduction in the absolute number of LUTs per device. The Virtex-5 series is a 65 nm design fabricated in 1.0 V, triple-oxide process technology.

Legacy Virtex devices (Virtex, Virtex-II, Virtex-II Pro, Virtex 4) are still available, but are not recommended for use in new designs.

Kintex
The Kintex-7 family is the first Xilinx mid-range FPGA family that the company claims delivers Virtex-6 family performance at less than half the price while consuming 50 percent less power. The Kintex family includes high-performance 12.5 Gbit/s or lower-cost optimized 6.5 Gbit/s serial connectivity, memory, and logic performance required for applications such as high volume 10G optical wired communication equipment, and provides a balance of signal processing performance, power consumption and cost to support the deployment of Long Term Evolution (LTE) wireless networks.

In August 2018, SK Telecom deployed Xilinx Kintex UltraScale FPGAs as their artificial intelligence accelerators at their data centers in South Korea. The FPGAs run SKT's automatic speech-recognition application to accelerate Nugu, SKT's voice-activated assistant.

In July, 2020 Xilinx made the latest addition to their Kintex family, 'KU19P FPGA' which delivers more logic fabric and embedded memory

Artix
The Artix-7 family delivers 50 percent lower power and 35 percent lower cost compared to the Spartan-6 family and is based on the unified Virtex-series architecture. The Artix family is designed to address the small form factor and low-power performance requirements of battery-powered portable ultrasound equipment, commercial digital camera lens control, and military avionics and communications equipment. With the introduction of the Spartan-7 family in 2017, which lack high-bandwidth transceivers, the Artix-7's was clarified as being the "transceiver optimized" member.

Zynq
The Zynq-7000 family of SoCs addresses high-end embedded-system applications, such as video surveillance, automotive-driver assistance, next-generation wireless, and factory automation. Zynq-7000 integrate a complete ARM Cortex-A9 MPCore-processor-based 28 nm system. The Zynq architecture differs from previous marriages of programmable logic and embedded processors by moving from an FPGA-centric platform to a processor-centric model. For software developers, Zynq-7000 appear the same as a standard, fully featured ARM processor-based system-on-chip (SOC), booting immediately at power-up and capable of running a variety of operating systems independently of the programmable logic. In 2013, Xilinx introduced the Zynq-7100, which integrates digital signal processing (DSP) to meet emerging programmable systems integration requirements of wireless, broadcast, medical and military applications.

The new Zynq-7000 product family posed a key challenge for system designers, because Xilinx ISE design software had not been developed to handle the capacity and complexity of designing with an FPGA with an ARM core. Xilinx's new Vivado Design Suite addressed this issue, because the software was developed for higher capacity FPGAs, and it included high level synthesis (HLS) functionality that allows engineers to compile the co-processors from a C-based description.

The AXIOM, the world's first digital cinema camera that is open source hardware, contains a Zynq-7000.

Spartan family
The Spartan series targets low cost, high-volume applications with a low-power footprint e.g. displays, set-top boxes, wireless routers and other applications.

The Spartan-6 family is built on a 45 nm, 9-metal layer, dual-oxide process technology. The Spartan-6 was marketed in 2009 as a low-cost option for automotive, wireless communications, flat-panel display and video surveillance applications.

The Spartan-7 family, built on the same 28 nm process used in the other 7-Series FPGAs, was announced in 2015, and became available in 2017. Unlike the Artix-7 family and the "LXT" members of the Spartan-6 family, the Spartan-7 FPGAs lack high-bandwidth transceivers.

EasyPath
Because EasyPath devices are identical to the FPGAs that customers are already using the parts can be produced faster and more reliably from the time they are ordered compared to similar competing programs.

Versal
Versal is Xilinx's 7 nm architecture that targets heterogeneous computing needs in datacenter acceleration applications, in artificial intelligence acceleration at the edge, Internet of Things (IoT) applications and embedded computing.

The Everest program focuses on the Versal Adaptive Compute Acceleration Platform (ACAP), a product category combining a traditional FPGA fabric with an ARM system on chip and a set of coprocessors, connected through a network on a chip. Xilinx's goal was to reduce the barriers to adoption of FPGAs for accelerated compute-intensive datacenter workloads. They are designed for a wide range of applications in the fields of big data and machine learning, including video transcoding, database querying, data compression, search, AI inferencing, machine vision, computer vision, autonomous vehicles, genomics, computational storage and network acceleration.

On April 15, 2020, it was announced that Xilinx would supply its Versal chips to Samsung Electronics for 5G networking equipment. In July 2021, Xilinx debuted the Versal HBM, which combines the network interface of the platform with HBM2e memory to alleviate data bottlenecking.