Yungtaek Jang

Yungtaek Jang is an electrical engineer at Delta Products Corporation in Fremont, California. He was named a Fellow of the Institute of Electrical and Electronics Engineers (IEEE) in 2016 for his contributions to efficiency optimization of AC-DC power supplies. He obtained BE from Yonsei University in 1988 in South Korea and then got his MS from the University of Colorado in 1991. In 1995, after four years of studying under mentorship from Robert W. Erickson and Dragan Maksimovic, Jang got his Ph.D. following successful defending of his thesis on "Application of Resonant Technique for Three-Phase High Power Factor Rectification and Integrated Magnetic Converters".

Dr. Jang is known worldwide as an expert in performance optimization of switch-mode power supplies for data processing and telecommunications equipment. He is the inventor of a number of power conversion circuits and techniques that have enabled significant efficiency and power-density improvements of ac-dc power supplies in a cost effective manner. Since 1998, power supplies that incorporate Dr. Jang's inventions have been massively deployed in server, networking, and telecom equipment made by IBM, HP, Dell, and Cisco, as well as in datacenters of major internet companies such as Google and Facebook. In the late-nineties, a typical efficiency and power density of ac-dc computer power supplies was below 80% and 5 W/in3, respectively. Prompted by the explosive growth of the Internet, large computer manufacturers started challenging power supply makers to improve performance of their power supplies.

Dr. Jang's research was instrumental in enabling his company to implement power supplies with across-the-load efficiencies in the 90-95% range and power densities in the 20-35-W/in3 range. In addition, his pioneering effort has inspired many industry and university researchers to start working on performance optimization of ac-dc power supplies. Dr. Jang's research focus has been on the performance optimization of single-phase ac-dc boost power-factor-correction (PFC) front-end converters that are an integral part of every ac-dc computer power supply. Specifically, in 1999 he proposed a novel soft-switching technique for the boost PFC front end that has enabled 40-50% loss reduction compared to its conventional counterpart. The invention employs an active-snubber approach to eliminate reverse-recovery-related losses of the boost Si fast-recovery rectifiers. In addition, due to zero-current-switching of the boost switch, this technique made possible cost-minimization by using IGBT devices instead of more expensive MOSFETs. This approach has been employed in all high-performance server power supplies built by Dr. Jang's company until the introduction of virtually reverse-recovery-charge-free SiC rectifiers in 2008. It is still used today in cost-sensitive applications and those requiring low EMI designs. With millions of power supplies deployed, this invention has contributed to significant cumulative energy savings.

Dr. Jang has also made a key contribution to improving power density of high-frequency ac-dc computer power supplies by proposing a unique approach for minimizing the size of the energy-storage (bulk) capacitor of the front-end boost PFC converter. Generally, ac-dc computer power supplies are required to maintain the regulated output(s) for 12-20 ms after a line-voltage drop out. In conventionally optimized power supplies, approximately 1-2 uF/W of storage capacitance is required to meet the hold-up-time requirement since only approximately 40% of stored energy is utilized.

In 2002, Dr. Jang introduced the hold-up time extension concept that reduces the required capacitance and, therefore, the bulk-capacitor size by approximately 50% without adversely affecting the conversion efficiency. In the proposed concept, an auxiliary boost converter, which is only active during line voltage drop outs, is employed to discharge approximately 80% of the store energy. This invention that has been extensively implemented in power supplies manufactured by Dr. Jang's company not only has enabled significant increases in power density, but also has brought about significant material savings. The hold-up time extension technique will gain even more importance in the next generation of computer power supplies implemented with GaN switches that will enable efficient switching at much higher frequencies. With the further reduction of power-stage components enabled by significantly increased switching frequencies, the size of the energy-storage capacitors that are required to handle hold-up time will become the major obstacle in increasing the power density to 100 W/in3 and beyond.

Recently, Dr. Jang has developed a low-cost three-phase low-harmonic rectifier that uses only two switches and yet matches the efficiency and input-current total harmonic distortion (THD) of the rectifiers that require at least six switches. This converter does not employ active input-current shaping which further reduces its cost and, due to zero-voltage-switching of the switches, it exhibits improved EMI performance. Dr. Jang also introduced a light-load efficiency optimization technique that significantly improves the efficiency of power converters at loads below 20% of full load. In addition, he is one of the pioneers in wireless charging of portable electronic devices by having demonstrated 4.5-W and 30-W battery chargers in 2000. Moreover, in 2014, the control concept of the wireless charger was extended to a series resonant converter and makes it possible to operate as a bi-directional battery charger for electric vehicles.

Dr. Jang is a prolific inventor who has been awarded 29 U.S. patents. In addition, he has published 90 papers, 33 of them in various IEEE Transactions. He received the IEEE Transactions on Power Electronics Prize paper awards for the best paper published in 1996, 2009, and 2013, respectively. The best evidence of the relevance and impact of Dr. Jang's work is that his work is highly cited by other researchers.