Template:AMD Ryzen Z1 series
Common features of Ryzen Z1 handheld APUs:
- Socket: FP7, FP7r2, FP8.
- All the CPUs support DDR5-5600 or LPDDR5X-7500 in dual-channel mode.
- L1 cache: 64 KB (32 KB data + 32 KB instruction) per core.
- L2 cache: 1 MB per core.
- All the CPUs support 20 PCIe 4.0 lanes.
- Includes integrated RDNA 3 GPU.
- Fabrication process: TSMC 4 nm FinFET.
| Branding and model | CPU | GPU | TDP | Release date | ||||||
|---|---|---|---|---|---|---|---|---|---|---|
| Cores (threads) |
Clock (GHz) | L3 cache (total) |
Core config[a] |
Model | Clock (GHz) | |||||
| Base | Boost | |||||||||
| Ryzen | Z1 Extreme | 8 (16) | 3.3 | 5.1 | 16 MB | 1 × 8 | 780M 12 CU |
2.7 | 9–30 W | May 2023[1] |
| Z1 | 6 (12) | 3.2 | 4.9 | 2 + 4 | 740M 4 CU |
2.5 | ||||
- ^ Core Complexes (CCX) × cores per CCX or Zen 4 + Zen 4c cores
Template documentation | Common place to discuss layout and style of the AMD APU tables at: Talk:List of AMD accelerated processing units |
 | You can . |
References
- ^ "AMD Introduces Ryzen Z1 Series Processors, Expanding the "Zen 4" Lineup into Handheld Game Consoles". amd.com. 2023-04-25. Retrieved 2023-05-11.