Analog verification

Analog verification is a methodology for performing functional verification on analog, mixed-signal and RF integrated circuits and systems on chip. Discussion of analog verification began in 2005 when it started to become recognized that the analog portion of large mixed-signal chips had become so complex that a significant and ever-increasing number of these chips were being designed with functional errors in the analog portion that prevented them from operating correctly.

Technical details
Analog verification is built on the idea that transistor-level simulation will always be too slow to provide adequate functional verification. Instead, it is necessary to build simple and efficient models of the blocks that make up the analog portion of the design and use those to verify the design. Those models are typically written in Verilog or Verilog-AMS, but could also be written in VHDL or VHDL-AMS. However, simply using a simple functional model is not sufficient. It is also necessary to build a comprehensive self-checking testbench, that thoroughly exercises the design and compare its response against a previously written specification for the design. Furthermore, this testbench should be applied in turn to both the model and the design. In this case, the design is represented with a transistor-level schematic. If both the model and the design pass all tests, and if the testbench is comprehensive, then this confirms that the model is consistent with the design and that the design is consistent with the specification.

Applying a comprehensive testbench to an entire analog functional unit such as an audio codec, power Management IC, Power Management Unit, serdes, or RF transceiver, represented at the transistor level, is impractical. So instead, the verification proceeds hierarchically. One first builds simple models and tests benches for individual blocks. The block-level test benches are used to confirm that models match the implementation of the blocks and that the implementation matches the block-level specification. Then testbenches are built for the entire analog functional unit and applied to the top-level schematic of that unit with the blocks represented with their now verified models. To further improve the tests, one can perform mixed-level simulation, where the testbench for the functional unit is applied with one or two blocks at the transistor level, and all others at the model level.