GDDR5 SDRAM

Graphics Double Data Rate 5 Synchronous Dynamic Random-Access Memory (GDDR5 SDRAM) is a type of synchronous graphics random-access memory (SGRAM) with a high bandwidth ("double data rate") interface designed for use in graphics cards, game consoles, and high-performance computing. It is a type of GDDR SDRAM (graphics DDR SDRAM).

Overview
Like its predecessor, GDDR4, GDDR5 is based on DDR3 SDRAM memory, which has double the data lines compared to DDR2 SDRAM. GDDR5 also uses 8-bit wide prefetch buffers similar to GDDR4 and DDR3 SDRAM.

GDDR5 SGRAM conforms to the standards which were set out in the GDDR5 specification by the JEDEC. SGRAM is single-ported. However, it can open two memory pages at once, which simulates the dual-port nature of other VRAM technologies. It uses an 8N-prefetch architecture and DDR interface to achieve high performance operation and can be configured to operate in ×32 mode or ×16 (clamshell) mode which is detected during device initialization. The GDDR5 interface transfers two 32-bit wide data words per write clock (WCK) cycle to/from the I/O pins. Corresponding to the 8N-prefetch, a single write or read access consists of a 256-bit wide two CK clock cycle data transfer at the internal memory core and eight corresponding 32-bit wide one-half WCK clock cycle data transfers at the I/O pins.

GDDR5 operates with two different clock types. A differential command clock (CK) as a reference for address and command inputs, and a forwarded differential write clock (WCK) as a reference for data reads and writes, that runs at twice the CK frequency. Being more precise, the GDDR5 SGRAM uses a total of three clocks: two write clocks associated with two bytes (WCK01 and WCK23) and a single command clock (CK). Taking a GDDR5 with 5 Gbit/s data rate per pin as an example, the CK runs with 1.25 GHz and both WCK clocks at 2.5 GHz. The CK and WCKs are phase aligned during the initialization and training sequence. This alignment allows read and write access with minimum latency.

A single 32-bit GDDR5 chip has about 67 signal pins and the rest are power and grounds in the 170 BGA package.

Commercialization of GDDR5
GDDR5 was revealed by Samsung Electronics in July 2007. They announced that they would mass-produce GDDR5 starting in January 2008.

Hynix Semiconductor introduced the industry's first 60 nm class "1 Gb" (10243 bit) GDDR5 memory in 2007. It supported a bandwidth of 20 GB/s on a 32-bit bus, which enables memory configurations of 1 GB at 160 GB/s with only 8 circuits on a 256-bit bus. The following year, in 2008, Hynix bested this technology with its 50 nm class "1 Gb" GDDR5 memory.

In November 2007, Qimonda, a spin-off of Infineon, demonstrated and sampled GDDR5, and released a paper about the technologies behind GDDR5. As of May 10, 2008, Qimonda announced volume production of 512 Mb GDDR5 components rated at 3.6 Gbit/s (900 MHz), 4.0 Gbit/s (1 GHz), and 4.5 Gbit/s (1.125 GHz).

On November 20, 2009, Elpida Memory announced the opening of the company's Munich Design Center, responsible for Graphics DRAM (GDDR) design and engineering. Elpida received GDDR design assets from Qimonda AG in August 2009 after Qimonda's bankruptcy. The design center has approximately 50 employees and is equipped with high-speed memory testing equipment for use in the design, development and evaluation of Graphics memory. On July 31, 2013, Elpida became a fully owned subsidiary of Micron Technology and based on current public LinkedIn professional profiles, Micron continues to operate the Graphics Design Center in Munich.

Hynix 40 nm class "2 Gb" (2 × 10243 bit) GDDR5 was released in 2010. It operates at 7 GHz effective clock-speed and processes up to 28 GB/s. "2 Gb" GDDR5 memory chips will enable graphics cards with 2 GB or more of onboard memory with 224 GB/s or higher peak bandwidth. On June 25, 2008, AMD became the first company to ship products using GDDR5 memory with its Radeon HD 4870 video card series, incorporating Qimonda's 512 Mb memory modules at 3.6 Gbit/s bandwidth.

In June 2010, Elpida Memory announced the company's 2 Gb GDDR5 memory solution, which was developed at the company's Munich Design Center. The new chip can work at up to 7 GHz effective clock-speed and will be used in graphics cards and other high bandwidth memory applications.

"4 Gb" (4 × 10243 bit) GDDR5 components became available in the third quarter of 2013. Initially released by Hynix, Micron Technology quickly followed up with their implementation releasing in 2014. On February 20, 2013, it was announced that the PlayStation 4 would use sixteen 4 Gb GDDR5 memory chips for a total of 8 GB of GDDR5 @ 176 Gbit/s (CK 1.375 GHz and WCK 2.75 GHz) as combined system and graphics RAM for use with its AMD-powered system on a chip comprising 8 Jaguar cores, 1152 GCN shader processors and AMD TrueAudio. Product teardowns later confirmed the implementation of 4 Gb based GDDR5 memory in the PlayStation 4.

In February 2014, as a result of its acquisition of Elpida, Micron Technology added 2 Gb and 4 Gb GDDR5 products into the company's portfolio of graphics memory solutions.

As of January 15, 2015, Samsung announced in a press release that it had begun mass production of "8 Gb" (8 × 10243 bits) GDDR5 memory chips based on a 20 nm fabrication process. To meet the demand of higher resolution displays (such as 4K) becoming more mainstream, higher density chips are required in order to facilitate larger frame buffers for graphically intensive computation, namely PC gaming and other 3D rendering. Increased bandwidth of the new high-density modules equates to 8 Gbit/s per pin × 170 pins on the BGA package x 32-bits per I/O cycle, or 256 Gbit/s effective bandwidth per chip.

On January 6, 2015, Micron Technology President Mark Adams announced the successful sampling of 8 Gb GDDR5 on the company's fiscal Q1-2015 earnings call. The company then announced, on January 25, 2015, that it had begun commercial shipments of GDDR5 using a 20 nm process technology. The formal announcement of Micron's 8 Gb GDDR5 appeared in the form of a blog post by Kristopher Kido on the company's website September 1, 2015.

GDDR5X
In January 2016, JEDEC standardized GDDR5X SGRAM. GDDR5X targets a transfer rate of 10 to 14 Gbit/s per pin, twice that of GDDR5. Essentially, it provides the memory controller the option to use either a double data rate mode that has a prefetch of 8n, or a quad data rate mode that has a prefetch of 16n. GDDR5 only has a double data rate mode that has an 8n prefetch. GDDR5X also uses 190 pins per chip (190 BGA). By comparison, standard GDDR5 has 170 pins per chip; (170 BGA). It therefore requires a modified PCB. QDR (quad data rate) may be used in reference to the write command clock (WCK) and ODR (Octal Data Rate) in reference to the command clock (CK).

GDDR5X commercialization
Micron Technology began sampling GDDR5X chips in March 2016, and began mass production in May 2016.

Nvidia officially announced the first graphics card using GDDR5X, the Pascal-based GeForce GTX 1080 on May 6, 2016. Later, the second graphics card to use GDDR5X, the Nvidia Titan X on July 21, 2016, the GeForce GTX 1080 Ti on February 28, 2017, and Nvidia Titan Xp on April 6, 2017.