PWRficient

PWRficient is a microprocessor series by P.A. Semi where the PA6T-1682M was the only one that became an actual product.

PWRficient processors comply with the 64-bit Power ISA, and are designed for high performance and extreme power efficiency. The processors are highly modular and can be combined to multi-core system-on-a-chip (SoC) designs, combining CPU, northbridge, and southbridge functionality on a single processor die.

Details
The PA6T is the first and only processor core from P.A. Semi, in two distinct product lines: 16xxM dual core and 13xxM/E single core. The PA6T lines differed in L2 cache size, memory controllers, communication functionality, and cryptography offloading features. P.A. Semi planned up to 16 cores.

The PA6T is the first Power ISA core designed from scratch in the previous ten years outside the AIM alliance, which included IBM, Motorola, Freescale, and Apple Inc. Since Texas Instruments was an investors in P.A. Semi, it was suggested that its fabrication plants would have manufactured the PWRficient processors.

PWRficient processors were initially shipped to select customers in February 2007 and were released worldwide in Q4 2007.

P.A. Semi was bought by Apple Inc. in April 2008, and closed development of PWRficient architecture processors. However, it will continue to manufacture, sell, and support these components for the foreseeable future due to an agreement with the US Government for some military applications. Some components of the P.A. Semi PWRficient were later integrated into Apple silicon.

Implementation
PWRficient processors comprise three parts:

CPU
PA6T
 * Superscalar, out-of-order 32-bit/64-bit Power ISA processor core
 * Adheres to the Power ISA v.2.04
 * Little endian or big endian operation
 * 64/64 kB instruction and data L1 caches. 32 GB/s bandwidth.
 * Six execution units including a double precision FPU and Altivec unit
 * Hypervisor and virtualization support
 * Maximum 7 W at 2 GHz
 * 11 million transistors, 10 mm² large @ 65 nm.

Memory system
CONEXIUM
 * scalable cross-bar interconnect
 * 1–8 SMP cores
 * 1–2 L2 caches, 512 KB – 8 MB large. 16 GB/s bandwidth.
 * 1–4 1067 MHz DDR2 memory controllers. 16 GB/s bandwidth.
 * 64 GB/s peak bandwidth
 * MOESI coherency

I/O
ENVOI
 * Centralized DMA engine, 32 GB/s bandwidth
 * 16–64 SerDes lanes
 * XAUI
 * PCI Express
 * SGMII
 * Offload engine for cryptography, RAID, TCP

Users

 * Curtiss-Wright planned the 1682M processor for its signal processing systems.
 * Mercury Computer Systems planned the 1682M processor for its signal and image processing systems.
 * NEC planned the 1682M processor for its storage array systems.
 * AmigaOne X1000 has the 1682M processor as CPU.