WDC 65C265

The Western Design Center (WDC) W65C265S is a 16-bit CMOS microcontroller based on a W65C816S processor core, which is a superset of the MOS Technology 6502 processor.

The W65C265S consists of a fully static W65C816S CPU core, 8 KB of ROM containing a machine language monitor, 576 bytes of SRAM, a processor cache under software control, eight 16-bit timers with maskable interrupts, an interrupt-driven parallel bus (PIB), four universal asynchronous receiver-transmitters (UARTs), a watchdog timer that fires a restart interrupt, twenty-nine priority encoded interrupts, a time-of-day clock, two sound generators, a bus control register (BCR) for external memory bus control, interface circuitry for peripheral devices, ABORT input for low cost virtual memory interface, and many low power features.

Features

 * Hi-Rel low power CMOS process
 * Operating ambient temperature range is 0 °C to +70 °C
 * Single 2.8 V to 5.5 V power supply
 * Static to 8 MHz clock operation, as well as 32.768KHz capability
 * W65C816S compatible CPU
 * 16 MB linear address space
 * Twenty-nine priority encoded interrupts
 * Four UARTS's
 * Time of Day (ToD) clock features
 * 8 x 16 bit timer/counters
 * Bus Control Register
 * Many bus operating features and modes
 * 8 Programmable chip select outputs
 * Low cost surface mount 84 and 100 lead packages
 * Automatically shifts speed for slow memory or peripherals