ARM Cortex-X2

The ARM Cortex-X2 is a central processing unit implementing the ARMv9-A 64-bit instruction set designed by ARM Holdings' Austin design centre as part of ARM's Cortex-X Custom (CXC) program. It forms part of Arm's Total Compute Solutions 2021 (TCS21) along with Arm's Cortex-A710, Cortex-A510, Mali-G710 and CoreLink CI-700/NI-700.

Architecture changes in comparison with ARM Cortex-X1
The processor implements the following changes:

Performance claims:
 * 10 cycle pipeline down from 11, created by reducing the dispatch stage from 2 cycles to 1
 * Reorder buffer (ROB) increased by 30% from 224 entries to 288
 * dTLB increased by 20% from 40 entries to 48
 * SVE2 SIMD support
 * Bfloat16 data type support
 * Support for Aarch32 removed
 * DSU-110
 * Up to 12 cores (up from 8 cores)
 * Up to 16M L3 cache (up from 8 MB)
 * CoreLink CI-700/NI-700
 * Up to 32MB SLC
 * ARMv9.0
 * Comparing the Cortex-X2 to the Cortex-X1 with the same process, clock speed, and 4MB of L3 cache (also known as ISO-process):
 * 16% greater integer performance / IPC
 * 100% greater ML performance
 * 30% peak performance improvement over the Cortex-X1 in smartphones (3.3 GHz, 1MB L2, 8MB L3)
 * 40% faster than an Intel Core i5-1135G7 at 15W (3.5 GHz, 1MB L2, 16MB L3)

Usage

 * MediaTek Dimensity 9000/9000+
 * Qualcomm Snapdragon 7+ Gen 2
 * Qualcomm Snapdragon 8/8+ Gen 1
 * Samsung Exynos 2200