Talk:Intel i960

Misinformation concerning i960 versus i432
I was on the i960 design team, wrote a compiler for it, ported UNIX to it, and later led one of the marketing teams. Many of the edits to this page have been from people who have only read about the i960 (and the i432). If you are going to expand the page, fine. But there is a lot of misinformation about the relationship of the i960 to the i432 floating around, and I don't want to see it promulgated here. gnetwerker - 1/1/05 — Preceding unsigned comment added by 7265 (talk • contribs) 21:14, 1 January 2005 (UTC)

Still in use today
This article leaves me with an impression that the i960 is not really in use to today. AFAIK, the i960 is in use in many high end Adaptec SCSI controllers. — Preceding unsigned comment added by 205.208.245.134 (talk) 23:00, 10 April 2005 (UTC)


 * Yes, you are right. Is in fact rare to see a true hardware RAID-5 capable hard disk controller from any vendor which does not use the Intel 960. In fact even the cheapish Adaptec AAR-2400A raid controller uses the i960RS to drive a RAID-5 array of four common paralel ATA hard drives. This niche merits a mention in the article. 82.131.210.162 — Preceding unsigned comment added by 82.131.210.162 (talk) 10:27, 29 June 2007 (UTC)

May still be in use by the F22 Raptor aircraft as part of its Common Integrated Processor avionics. ''The modular, fault-tolerant F/A-22 CIP configuration employs up to 66 PowerPC and i960-based signal and data processor modules, all interconnected for efficient sharing of computational tasks.'' www.raytheon.com/capabilities/products/f22_cip/ --Rsquid (talk) 17:23, 7 January 2011 (UTC)


 * Link is dead, but here's a slightly older one: . It's not clear whether the F-22 still uses the i960MX or whether it's transitioned entirely to PowerPC now. Cfmdobbie (talk) 19:24, 4 May 2019 (UTC)

Rumors
When I was doing i960 support for Intel in the late 90s, there was a rumor floating around about Windows 3.1 being ported to the i960CX and it vastly outperforming the i386. The project was supposedly canned because "we're in the business of selling x86, not 960". Can anyone confirm this rumor? Billbrasky 19:50, 27 September 2005 (UTC)

This is not true. It maybe a result of the fact that the i860 did have a version of Windows ported to it, though I think it was WindowsNT. I ported UNIX to the original i960, but Intel decided not to sell the memory-managed version of the chip (MC) to the commercial market (saying something like the quote you relate), so this went nowhere, and the later i960CA lacked an MMU altogether. So the rumor reflects an underlying truth, but is not in detail correct. -- Gnetwerker 21:28, 28 September 2005 (UTC)

P.s. -- BTW, my somewhat fuzzy recollection was that it was Dave House who, failing to be convinced by Glen Myers, put the kibosh on the i960 as a UNIX machine, fearing competition and distraction. (As much as I hated the decision at the time, in retrospect it was probably correct.) In any case, I got the impression from Glen that Andy Grove ratified the decision. House led the 386 marketing team at the time, that being 1986. Had Steve Jobs chosen the chip for the Next machine, things probably would have worked out differently. -- Gnetwerker 21:33, 28 September 2005 (UTC)

Variant updates
I'm going to update a few of the sections including the processor variants, as it is missing a few keys things - like the SA version and HD version. I would also like to add a simple table of the variants and key differences since they are somewhat unique for a given purpose. Let me know if this does not sound like a good addition. Sponaugle (talk) 02:45, 17 May 2022 (UTC)

I added the few missing variants (in particular the Hx and Rx). I'd like to add a table of the variants and a few key parameters, similar to what exists on other processors pages. Any comments on this idea? Sponaugle (talk) 14:16, 17 May 2022 (UTC)

I added a set of tables that shows some of the key attributes and differences across the variants. I broke the tables into 3 sections: 5V, 3.3V, and PCI IO Devices, which seemed like a logical division given the part distribution and history, but happy to take comments on that approach. On thing missing from the table is the presence of the FPU, which could be added. Sponaugle (talk) 16:19, 17 May 2022 (UTC)

Originally-for-BiiN i960 model with segmentation and object descriptors - 960MX, or something else?
The BiiN CPU Architecture Reference Manual describes the processor used in the BiiN designs; the instruction set is the i960 instruction set, but with segmented addressing and object descriptors. That sounds like the 80960 "extended architecture" mentioned in "Crafting An Ada Executive for the Intel 80960 Extended Architecture"; that paper speaks of "Ada-960MX" as being a cross-development system for the "extended architecture" processor, and gives, as a reference, "Military i960(TM) MX Microprocessor Overview"

The description of register scoreboarding in the BiiN manual on page 2-3 is similar to the description of register scoreboarding in the http://www.bitsavers.org/components/intel/i960/271080-006_80960MC_Advance_Information_Jan91.pdf 80960MC Advance Information data sheet] on page 7. Neither appear to be fully superscalar, but do allow execution of instructions not involving the register being loaded to occur while waiting for a load to a register to complete.

So are there any sources that indicate whether the "MX" version was a superscalar implementation of the extended architecture or just the full extended-architecture version of the first generation of 960 processors? (And what was the "XA"?) Guy Harris (talk) 09:21, 24 April 2023 (UTC)


 * The early i960 models fall into four categories: "core architecture", the basic processor; "numerics architecture" with an FPU, "protected architecture", also adding virtual memory and task management; and "extended architecture", adding the 33-bit tag-based object system, based on the iAPX 432.
 * The original BiiN chip provided the full extended architecture, but then the identical die was sold as the 80960 for all four architectures. These were the KA, KB, MC, and XA models respectively.
 * This was followed by the SA (core) and SB (numerics) models. These used the original chip design, slightly modified to use a 16-bit bus. (A bit like the 8088 vs 8086.) This layout spread out the bond pads better, eliminating the NC pins and allowing a smaller package. But it limited the maximum speed.
 * Next, the CA and CF were the superscalar models, both core architecture (no FPU). This was a complete redesign. The design was improved a bit and a new FPU added along with extra features to form the military MM (protected) and MX (extended) chips.
 * I'm still researching all this to find good sources. KenShirriff (talk) 21:27, 26 April 2023 (UTC)