Talk:PDP-11 architecture

Article split off from PDP-11
I've split the architectural information off from the PDP-11 article to form this one; for more details, see Talk:PDP-11. Be aware that top-level sections are now pointed to by links in PDP-11. --Spike-from-NH (talk) 00:29, 15 February 2009 (UTC)


 * Shouldn't the "PDP-11 Lore" section be on the main page? -- Resuna (talk) 01:13, 16 November 2015 (UTC)


 * Going just by the section title, sure. But the content in that section is about the increment and decrement addressing modes, which are definitely part of the architecture and described here; the content wouldn't make any sense to someone who had only read the main page. Maybe the section title should be changed to not suggest that it's about "PDP-11s in popular culture". Jeh (talk) 19:36, 16 November 2015 (UTC)
 * I retitled the section "Myth of PDP-11 influence on programing languages" to make its signifigance clear.--agr (talk) 03:40, 17 November 2015 (UTC)

CPU registers infobox
I've added the "CPU Registers" infobox to several articles now (see 4004, 4040, 8008, 6800, 6502, 8080, Z80, 68000, 8086, PDP-8, PDP-11 architecture), using the original one in the 8086 article (a few revisions back) as a template. I've reverted this edit which removed the "Instruction pointer" and "Stack pointer" components in the infobox. My goal is to find a consistent nomenclature within the infobox suitable for all processors, whether the designers/users of a given CPU used those terms or not. For example, some CPUs have an "instruction pointer" (IP) while others have a "program counter" (PC). TO be consistent, the infobox should show the same title for that register (e.g., "Instruction pointer"), but can show the (possibly different) CPU-specific name for the register to the right of the register itself (e.g., "Program Counter" or "R7"). Discussion? — Loadmaster (talk) 22:14, 19 June 2013 (UTC)


 * Your goal of "consistent nomenclature" is inconsistent with WP:V. You will not find a single document in the PDP-11 or VAX library from DEC that uses the term "instruction pointer." WP must follow the nomenclature used in its sources, and if sources for one manufacturers' architecture use different terms than those for another manufacturer, WP must follow suit. Indeed, it is practically WP:OR on your part to say that the VAX "program counter" is the same thing as the Intel "instruction pointer," or to choose the latter as WP's "standardized" term. WP is not in the business of choosing standardized names for things when the industry has not. Jeh (talk) 23:06, 19 June 2013 (UTC)


 * And yet every infobox has a set of titles for each displayed component (e.g., "Birth place", "Nationality", "Genre", "Preceded by", etc.), presumably agreed upon by some group of WP editors. Why can't the same be applied to CPU register tables? And FWIW, I don't really care what we call each CPU component, just as long as we're consistent across articles. Also note that we are including the manufacturer's name for each register (e.g., "R0", "D0", "A0", "PC", "IP", whatever), we're just also labeling them with a more common term for reader comprehension. Consider how a reader might compare the architectures of different CPUs, especially from different hardware eras. While it's true that what I added are just tables, it would be nice to move to an infobox-like type of WP markup. Things like future microformats for this sort of thing should also be considered, which do require a common agreed-upon nomenclature. — Loadmaster (talk) 00:00, 20 June 2013 (UTC)


 * Please. Legends such as "Birth place", etc., are common terms. But here we're talking about technical terms. Until you find a WP:RS (preferably a DEC manual) for the PDP-11 program counter being called an "instruction pointer", we can't call it that. It's as simple as that. Yes, that means there will be different terms used in articles about CPUs from different manufacturers. It is easy enough, in the PDP-11 and VAX articles, to write "the Program Counter (PC) register contains the address of the next instruction to be executed", and in the Intel-ish articles, "the Instruction Pointer register contains the ...." But you can't decide for all of WP's readers that "instruction pointer" is a generic term that can be used for both. In fact there is at least one key difference between how the VAX and PDP-11 use the PC register and how the Intel-ish processors use the IP (or EIP, or RIP), a difference that is obscured by saying or implying "well, the Program Counter is really just DEC's version of the instruction pointer." It isn't, and you shouldn't be saying that it is. Jeh (talk) 00:47, 20 June 2013 (UTC)


 * I agree with Jeh. If you write a PDP-11 program that references a general-purpose register as IP or HL, it simply won't assemble.  The desire for the whole world to fill out the same form is foolish consistency, given that we are documenting products whose terminology was expressly inconsistent. One target audience is readers with PDP-11 experience, and it would be gratuitously baffling for this article to describe to them the PDP-11 in the terminology of some other vendor, based on some standard language we adopted 30 years after-the-fact. Spike-from-NH (talk) 04:00, 20 June 2013 (UTC)
 * PS--Let me retract part of that. The risk is not that we will cause PDP-11 assemblies to fail. The risk is merely that selecting nomenclature unfamiliar to that target audience means we won't be communicating as clearly as we could. Spike-from-NH (talk)


 * I see your point. However, the target audience is not limited to PDP-11 users; take me, for example, a programmer who who cut my teeth mainly on the 8080, 6502, S/370, and 8086, and who is simply curious about the PDP and other older computers. Also note that there are two ways of "communicating as clearly as we can", which is either to use the nomenclature of the CPU manufacturer, which is inconsistent between vendors, or to use the most commonly accepted modern terms to communicate with. We're not arbitrarily choosing one vendor's terms over all the others, but rather trying to find the most commonly used terms that the largest audience will comprehend. FWIW, I personally think more people understand the term "program counter" than the alternatives "instruction pointer" (Intel) or "instruction address" (IBM). Indeed, that's what the WP article is titled. But since you seem to think I'm pushing an agenda other than clear communication, and therefore we can't reach a consensus, feel free to change the table labels as you like. — Loadmaster (talk) 21:44, 20 June 2013 (UTC)


 * It's not that we think you're pushing an agenda, it's just that your arguments are not supported by WP policy. Verifiability (WP:V) is a key policy. If you can't find a reliable source (WP:RS) that says that DEC called this register on PDP-11's or VAXes the "instruction pointer", then you or any other editor can't make that leap, no matter how much you think it improves communication. To do so is borderline original research (WP:OR) on your part. Which is forbidden.


 * Also, please note that consensus (WP:CON) on WP is not based on voting, nor on getting everyone to agree. It is based on reasoning that is based on WP policy. Your argument is not based on WP policy that I can see. There is no WP policy I'm aware of that supports using technical terms not found in a relevant WP:RS just because an editor thinks they'd improve communication. There are other places (like Wikibooks) where you are free to make any leaps of reasoning you like, but WP is not one of them. Jeh (talk) 01:42, 21 June 2013 (UTC)


 * I've decided to change all of the CPU register tables to use "Program counter" (instead of "Instruction pointer", "Instruction address", or whatever) for consistency. I've changed all the tables that I've added to date, including the PDP-11 table. — Loadmaster (talk) 22:37, 26 August 2013 (UTC)


 * *sigh* This would be inappropriate for e.g. x86, where it's called the instruction pointer. Your desire for consistency does not trump sources. If the source for information on x86 calls it the "instruction pointer" (and it does), then that's what we have to call it. After all the assembler mnemonic is EIP or RIP. Jeh (talk) 02:22, 27 August 2013 (UTC)

Reliance on sources does not mean we can't use universally common terms for things like CPU registers, especially since we have WP articles dedicated to those terms. We can use the common terms for the register groups in the infoboxes, but use the CPU-specific mnemonics for the actual register names. So we could use the terms "Program counter", "Index registers", etc. to label the register groups in the tables, but then use the manufacturer's names (e.g., "R7", "PC", "IP", "IX", "AH", etc.) beside the depictions of the individual registers. I think this provides us with a more understandable, certainly more consistent, way to present the info to readers. Linking the labels to their corresponding articles (e.g., Program counter, Status register, Carry flag) would help, too. Using the names of the existing WP articles for the CPU elements would appear to make sense when describing these features for all CPUs. The term "instruction pointer" within the Intel 8086 article should link/redirect to the "program counter" article. — Loadmaster (talk) 16:49, 27 August 2013 (UTC)


 * Part of the issue with what you're proposing is that there is no "universally common term." Someone who had worked in the DEC space all their lives might never have heard of anything called an "instruction pointer." A Wikipedia article should not contradict its own references and should, as much as possible, be internally consistent. What you are proposing will create confusion, as the reader tries to understand why the spelled-out name is "program counter" but the mnemonic name is "EIP".. and the references call it "extended instruction pointer." Of course the corresponding article does have to use a single name for its title (and that article would list the several names that have been used for this register over the decades), but this and similar articles should not create confusion that requires another article to sort out. A student of computer architecture could be expected to read many of these architecture articles, but what of the person who just wants information about x86-64? In any case it is not WP's job to choose and impose an industry-wide naming convention in the architecture-specific articles. It is WP's job to report on the names the industry uses. Jeh (talk) 17:13, 3 September 2013 (UTC)


 * There would also be practical difficulties with trying to use generic names eg: core architectural dedicated registers that don't exist even conceptually on some CPUs, such as the Transputer "Workspace Pointer" register (also found on TI9900 but not on any x86/SPARC/MIPS/etc), and the Transputer dedicated "Operand Register" (sequentially loaded 4-bits at a time), and there will be other examples too. Generic register naming suffers from the "all the World's a VAX" syndrome. Shelldozer (talk) 17:31, 19 September 2017 (UTC)
 * Note that Wikipedia commonly asks for secondary and tertiary sources. While the primary source (DEC) might have some names for them, it might be that other sources use different names. Those names could then, with proper reference, be used here. There are some words that are common terms in the art, so common as to not need specific references. Gah4 (talk) 11:03, 11 January 2021 (UTC)
 * Note that Wikipedia commonly asks for secondary and tertiary sources. While the primary source (DEC) might have some names for them, it might be that other sources use different names. Those names could then, with proper reference, be used here. There are some words that are common terms in the art, so common as to not need specific references. Gah4 (talk) 11:03, 11 January 2021 (UTC)

Mapping general registers to memory addresses
added the following text to the article and took it back out:


 * On older system (with hand-switches - like the PDP 11/05 and 11/10) the registers R0-R7 are available on the bus at memory address 0x177770-0x177777, and can be read and modified on the handswithes via those bus addresses. I dont know if this 'feature' continued in later models. On 18 and 22 bit architectures the 0x1 would need to be extended.

I agree that the text needs refinement and especially the use of "I" is un-encyclopedic. But the bigger problem is that the material is hardly about "architecture." Indeed, in the oldest PDP-11s, you could enter these uppermost addresses on the sense switches to read and modify the general registers. However, more importantly, you could not use this apparent mapping to the memory space in a program. #177775 is an odd (byte) address and it would be remarkable and dangerous if it gained access to the word in R5. Long before PDP-11s went to 18 and 22 bits, console debugging supplanted debugging via sense switches, and this hack was not carried forward.

Far from an essential aspect of "PDP-11 architecture", this use of the sense switches was a bridge to an even earlier age, when a processor with 8 general registers would require 8 rows of incandescent lamps for debugging. Spike-from-NH (talk) 00:53, 23 July 2018 (UTC)


 * Yes, this doesn't seem to be part of the architecture, but part of some implementations of the architecture. This is unlike the PDP-10, where the registers (ACs) are part of the user address space. If there are articles on the specific implementations, it could go there. Gah4 (talk) 01:36, 23 July 2018 (UTC)

I am unaware of articles on the individual models, and the list of models at PDP-11 does not include links to separate articles. Spike-from-NH (talk) 03:10, 23 July 2018 (UTC)


 * For the record, I don't think such articles should exist. Many of the models differ in only small details. What would be helpful would be if the "list of models" at PDP-11 explained more context as to how and why they differed, why so many different ones existed, when various models were discontinued, etc. Jeh (talk) 04:56, 23 July 2018 (UTC)


 * Oh, yes. I put the If, but maybe with not enough emphasis.  Sometimes one model of a series will be enough different to get its own article.  The IBM 360/91 is a favorite for just about any book on pipelined processors, and probably deserves its own article. I don't know for the PDP-11, though, which ones should have an article. Gah4 (talk) 20:46, 23 July 2018 (UTC)

Description of File:Papertape.jpg
Hi, I hope someone here may know this. The description of File:Papertape.jpg reads: "paper tape used to store data and computer programs in the 1950's". PDP-11 did not exist in the 1950-s (even PDP-1 hardly existed). Is this a typo in the description and it should by "1970's" instead? Tzafrir (talk) 15:11, 13 October 2019 (UTC)
 * The file description is not decisive. Paper tape did exist (I'm not sure of the chronology) but mostly spools.  A common use was the TeleType, which could use paper tape as an alternative source to the keyboard and alternative destination to the printer.


 * The photo itself shows the DEC "fan-fold" paper tape, and early PDP-11s did have a reader near the console. The tape unfolded from a receptacle on one side of the reader and neatly refolded in a receptacle on the other side.  This is certainly not from the 1950s.  Perhaps File:Papertape.jpg should have its description changed to say what it's an actual photo of, rather than merely have a general statement of what paper tape was.  Spike-from-NH (talk) 20:15, 13 October 2019 (UTC)