Talk:POWER1

The following is copied from User talk:Rilak/02, where it resided as the article was being readied for release: Rilak (talk) 11:05, 27 August 2008 (UTC)

Include
-- Henriok (talk) 10:55, 7 August 2008 (UTC)
 * Names: RIOS, RIOS-1 and RIOS.9.
 * Further development: RSC, PowerPC 601 and RAD6000

Done. Not sure what RIOS is though. Rilak (talk) 11:48, 7 August 2008 (UTC)

To do
in order...
 * include some stuff about the branch predictor. I found a nice link (it's in the references). I don't know where it fits, but I think it's in the ICU.
 * Release!
 * Add boxes and templates
 * Redirect other articles
 * Rewrite some other articles
 * Find online references

Difference?
What is the difference between the RIOS1, RIOS-1 and the RIOS.9? These terms are not mentioned in the literature listed in the "references" section. Also, I have found this, which suggests that for a time, POWER2 was called RIOS2, which would mean that upgraded versions of the POWER1, the POWER1+ and POWER++ may also have RIOSn names before the introduction of the POWERn scheme. I would like to know the original names for the POWER1+ and POWER1++ so that they can be mentioned in the article. Rilak (talk) 07:13, 18 August 2008 (UTC)
 * RIOS1 and RIOS-1 are probably the same thing. POWER1+ and ++… I have no idea. RIOS2 is POWER2 and is explained in the docs to GCC as the target for POWER2 is called RIOS2. What does RIOS stand for? Where is an old IBMer when we need one?-- Henriok (talk) 19:31, 18 August 2008 (UTC)
 * So which one do we use when reffering to the full version of the POWER1? "RIOS1" or "RIOS-1"? Rilak (talk) 10:59, 19 August 2008 (UTC)

POWER1++?
This PDF says: "The last POWER1 machine, announced in September of 1993, was the rack-mounted Model 990. It ran at 71.5 MHz and had a 32 KB I-cache and a 256 KB D-cache." It's presumably the POWER1++, and has four times as much I- and D-cache as RIOS-1. However.. this sounds very much like the POWER2. Is is possible that POWER++ _is_ the RIOS2, i.e. POWER2? -- Henriok (talk)


 * The quoted statement may be a mistake. According to this source, the Model 990 is a POWER2-based system, not a POWER1++. The source of course, is unofficial so it does not determine anything, it just points out that we need to do so more research. Where are the old IBMers when we need one? :) Rilak (talk) 10:58, 19 August 2008 (UTC)

Chip count
Figure 2 in The IBM RISC System/6000 processor: Hardware overview shows 11 chips. We can easily account for 10 of them and what's in question is why the I/O unit sems to be split into two chips. For one, the SIO bus seems to be a double bus, and if onw takes a look at the POWER2 chip complex they are similar and they show two I/O units represented by two chips (off MCM). On page 7 in POWER2 Next generation of the RlSC System/6000 family it says that "The  POWER2 I/0 unit  is the same as the one in the RS/6000 Models 580 and 980", which are POWER1 based.. Even if it's clearly "original research" in Wikipedia terms, I think we can assume that the I/O unit in POWER1, at least in the 580 and 980 models, consists of two chips. So.. I should probably revise the diagrams showing two I/O units and a Clock-chip. -- Henriok (talk) 16:03, 21 August 2008 (UTC)
 * 1) FX = FXU
 * 2) FP = FPU
 * 3) D = D-cache
 * 4) D = D-cache
 * 5) D = D-cache
 * 6) D = D-cache
 * 7) I = ICU
 * 8) S = SCU
 * 9) C = I/O unit
 * 10) C = I/O unit
 * 11) CLK = CLK


 * The chip count is rather confusing. In "The IBM RISC System/6000 processor: Hardware overview" on page eight, Table 1 shows the transistor count and die sizes for each chip. Notice that the entry for the DCU has "× 4"? The IO unit does not have this, implying that it is on one chip. A possibility is that the "Buffer", as shown in Figure 4 on page seven is the second "C" chip, but I'm just speculating. If we are to revise the article to reflect this, what about the the transistor count and die sizes for the I/O unit? Would the given figures be for both chips or just one? I know that IBM has more detailed technical information with their "IBM RISCSystem/6000 Technology" book that may help give a more conclusive answer, but I have not found freely assessable copies yet. Rilak (talk) 08:23, 22 August 2008 (UTC)


 * I have read "The IBM RISC System/6000 processor: Hardware overview" more closely and I have good reason to believe that the second "C" chip is the buffer. Firstly, Figure 1 on page two shows a block diagram of the central electronics complex. Notice that all of the blocks (excluding the I/O related ones) represent a chip? However, the I/O unit is also connected to a block labeled "TWC RAM" and "Buffer". If we examine Figure 2, the CPU planar board shows the TCW RAM as discreet components. Therefore, the "Buffer" is likely to be the second "C" chip. The component labeled "IPL" I think is the "Initial Program Load" ROM, as I have heard that IBM refers to the term as "IPL". The "Storage control unit" section on page seven mentions it being interfaced to the SCU, which would fit in to its purpose as it is the SCU that controls the CPU. It would be ideal for start up ROM to be connected to the SCU. However, the statement states "ROS" instead of "ROM" which may be IBM terminology for the same thing or a misspelling. If this does prove to be correct or acceptable given the resources we have at the moment, I am happy with releasing the article and continuing any improvements at the article. Rilak (talk) 12:59, 26 August 2008 (UTC)
 * How does this relte to the transistor count of the I/O unit which in Table 1 only lists one chip for the I/O unit? There's buffers mentioned in relation to the Serial Link Adapters in the I/O section byt they are 2x265 bytes large, hardly enough to constitute a chip of any respectable size, even if there's many SLAs. I think the I/O buffer is included in either the I/O chip or is a small chip not included or labled in Figure 2. There's 200 000 transistors in the I/O chip for memory, are these used for the I/O buffer? The Models 580 and 980 mentioned in the POWER2 paper which supposedly is configured with two I/O units, is not mentioned in the POWER1 document, but there can still be traces of them, like in Figure 2. I think there's one I/O unit, using one chip, and the one chip labled "C" which is missing in action is an optional, later or scrapped version. I'm leaning towards that RIOS-1 only uses 9 chips (RIOS.9 uses 7), and in light of the info given in the POWER2 document there are some high end configurations that uses two I/O units to a total of 11 chips (buffer chips not included).
 * Conclusion: We do not include a chip count in the article. The I/O subsection remains as it is. The current graphics stands, and we release the article as it is. If there are some errors in the documentation, or unclarities which we cannot sort out, it's too bad, but we have made the best we could. Some expert might come out of the woodwork when we publish but I doubt it. It's mostly correct, I'm certain. If the article is disputed, we have this discussion to lean on, and as a starting point for further research. I say release! -- Henriok (talk) 08:13, 27 August 2008 (UTC)

Well, I remember that the lowest-end machine had two less chips than the rest of them; I presume it was the D-cache. Although I could have sworn it was 9 and 7 not 11 ... linas (talk) 21:29, 26 August 2012 (UTC)
 * As you can see in my diagrams, the chip complex are 7 (RIOS.9) and 9 (RIOS-1) chips. I left the CLK out (I can't remember why), and the question stands if the I/O units are one or two, and if they should count towards the chip count. If you look at this picture is shows 8 chips. It's confusing… :) I look forward to your analysis. I consider you one expert that has come out of the woodwork! – Henriok (talk) 09:35, 27 August 2012 (UTC)

FPU/FXU
I'd like to see more about how the FPU differed from the competition. At the time, it seemed rather revolutionary; when running misc codes in the lab, it would be done so fast, that at first, I thought there was a bug in the code or a bug in the OS. (as compared to e.g. SGI of the era, or HP or Sun). linas (talk) 21:33, 26 August 2012 (UTC)
 * That's a great suggestion. I followed your previous discussion and it seems to be in order. I'm not at all confident in that I could write such an addition, but you seem to be. I think two or three sentences would strike a good balance in regard to the rest of the article. -- Henriok (talk) 09:21, 27 August 2012 (UTC)