Talk:Quad data rate

Untitled
Two clock signals 90 degrees out of phase? that sounds hard enough to do on a single die, much less maintaining that for an external bus!

There seems to be some support for the dual clocks at this page on NEC's research. But I can also find documents that say QDR is actually quad only because the read and write channels are separate, DDR each. There's two different documents, one from Altera, and one from PCkado (in French).

I think the document should be updated to reflect this; it seems there may be two QDR's. Which one should get the actual moniker, if not both? -- DougLuce


 * Is it a misconception when intel or people that sell intel chips say that the front side bus is 1333 or 1600 MHz? It seems to me that they are 333 or 400 MHz but are "quad pumped". I think that this article should reflect that if it is true.
 * Also what is the relationship between maximum transfers per second and MHz? If I am reading this article correct a 400MHz "quad pumped" chip should have a maximum transfer rate of 1600 million transfers / second.  -- MattC  —Preceding unsigned comment added by Mcot (talk • contribs) 16:46, 28 June 2008 (UTC)


 * From what I have read, it seems the "two clock signals" description is a theoretical model, and real implementations use a phase locked loop at four times the frequency to generate these theoretical "two clock signals 90 degrees out of phase." -- CmdrRickHunter (talk) 02:09, 9 September 2014 (UTC)

How quad data rate can be useful if GPU working on 1/4 of GDDR frequency?

 * Are you thinking your head? There is many GPU's which have clock speed about 1000 MHz and GDDR (quad data rate) working on 4000-6000 MHz. What is use from quad channel if GPU can't afford such frequency to take data at such speed from VRAM? — Preceding unsigned comment added by Paraboloid01 (talk • contribs) 19:12, 27 September 2012 (UTC)
 * I meant quad data rate instead quad channel. But speaking about quad channel, it could be useful for quad-core CPU or for 256-bit AVX. But SSE and AVX have very very limited number of applications, where need such precision (4 dimensional vector of 64 bits each dimension precision for graphics like colors is not needed). But there is even a question if AVX don't need 4 times more cycles for x87 FPU. — Preceding unsigned comment added by Paraboloid01 (talk • contribs) 19:28, 27 September 2012 (UTC)
 * GPUs do many operations in parallel. They often have multiple texture units which can make multiple memory requests per calculation.  This parallel activity can quickly saturate even a 6Ghz GDDR memory bus, which is why they often maintain caches on the GPU processor.  CmdrRickHunter (talk) 02:03, 9 September 2014 (UTC)

Benefits over DDR
It would be nice with an explanation of when and why QDR is used instead of DDR (with twice the fundamental clock rate, that is). Since the actual data-carrying circuits need to be able to switch twice as fast as the clock-carriers anyway, it doesn't seem to be because of fundamental timing constraints, right? If so, what are the actual benefits (under what circumstances)? --Dolda2000 (talk) 03:53, 2 July 2013 (UTC)


 * I had the same confusion, and found very little documentation on the matter. Finally, I found that the Intel patent application for their QDR technology had the answers.  I added a short section with what I found.  I hope it helps! --CmdrRickHunter (talk) 02:05, 9 September 2014 (UTC)


 * Great addition to the article! It would be good to explain the strobe signal further, if possible. &mdash; Dsimic (talk | contribs) 01:32, 11 September 2014 (UTC)

Requested move

 * The following discussion is an archived discussion of a requested move. Please do not modify it. Subsequent comments should be made in a new section on the talk page. Editors desiring to contest the closing decision should consider a move review. No further edits should be made to this section. 

The result of the move request was: I've gone ahead and closed this discussion as page moved. This, as User:BDD states, is a non-controversial application of WP:CAPS, which probably didn't need an RM anyway. But due diligence and caution is appreciated. Tyrol5  [Talk]  03:26, 13 February 2013 (UTC)  Tyrol5   [Talk]  03:26, 13 February 2013 (UTC)

Quad Data Rate → Quad data rate – not a proper noun per WP:CAPS, and matching Double data rate Widefox ; talk 08:53, 5 February 2013 (UTC)
 * Support per WP:NCCAPS. Not controversial. --BDD (talk) 21:11, 12 February 2013 (UTC)

QDR is a proprietary name
"QDR is a  registered  trademark  of  Cypress  Semiconductor  Corp" according to a white paper at http://www.cypress.com/QDR-IV_SRAM_Whitepaper. Syrely it should be marked as such in the text of the article. Guffydrawers (talk) 20:20, 9 November 2015 (UTC)

Aims & means clarification please
"The reasons for operating in QDR rather than DDR are very different than those cited for operating in DDR rather than single data rate" Are they? In both cases the aim is higher transfer rate, and possibly slightly lower latency. In both cases the means are multiplying transfer signal frequency (without raising the main clock) ; shorter transaction duration ; and better signal control. Both are a form of Pumping_(computer_systems), DDR is just simpler to do than QDR. Musaran (talk) 13:16, 21 June 2023 (UTC)