Talk:Silvermont

Page Structure
I'm looking for input into how to best structure this page. The silvermont microarchitecture will be used in several different SoC families(Bay Trail-T, -D, -M, and -I, Merrifield, Avoton, and Rangeley), all having significantly different structures and capabilities. As well as multiple brands(Atom, Celeron, and Pentium). I'm unsure if it is best to have all of the information on this single page, or if it would be better to break it into separate pages.2601:1:9C80:82:35CA:1F43:97D7:3AB0 (talk) 14:25, 15 July 2013 (UTC)

Devices based on these SoCs
Please, add devices which use these SoC's, for instance the Asus T100 which uses Z3740. Artem-S-Tashkinov (talk) 21:23, 27 October 2013 (UTC)


 * That already exists on another page, please feel free to update that page with new information if you have it. 2601:1:9C80:82:C1BF:B5EF:84E0:8D31 (talk) 06:00, 21 December 2013 (UTC)

Bay Trail-T Max Display Resolution
Can someone please provide reference for the max display resolutions in the tablet section. I can not find it in the datasheets or the spec update Leobdy (talk) 12:40, 22 October 2014 (UTC)

L2 cache for 2-core Airmont versions is WRONG
The Airmont section (as well as the [[List_of_Intel_Celeron_microprocessors#.22Braswell.22_.2814_nm.29|List of Celerons#Braswell) show all the Braswell SKUs having 2 MB cache. This is wrong, although Intel's own ARK shows it too (e.g. http://ark.intel.com/products/87257).

Each Airmont module contains 1 MB L2 cache and 2 cores. The 2-core versions have one defective/disabled Airmont module, so they cannot possibly have 2 MB L2 cache. CPUworld gets it right even though Intel's own ARK gets it wrong :-( 66.87.112.239 (talk) 05:08, 14 July 2015 (UTC)


 * Alright, that makes sense since L2 cache is usually tied to the number of cores. --Vossanova o&lt; 14:38, 14 July 2015 (UTC)