Talk:SystemVerilog

Blog section "SystemVerilog vs mixed Verilog/C++"
This entire section reads like a personal blog entry. It should be removed.

-> I entirely agree. This sounds like the screed of a petulant child. I sympathize with the author's point that SystemVerilog's touted advantages are nowhere near as clear as its advocates and the EDA vendors tout - and I work for a consulting company that promotes it. It is debatable whether that point is appropriate to a Wikipedia entry on the topic. But assuming the point is worth making here, the following blatant falsehood betrays the author's lack of objectivity:

"However, it should be noted that anybody skilled enough to write a mixed Verilog/C++ testbench can easily migrate to SystemVerilog environment with less than a day of effort due to the great similarity between the old method of mixed Verilog/C++ and SystemVerilog"

That's just a silly, misinformed statement.

74.12.117.218 (talk) 03:24, 17 August 2011 (UTC)

Whence UVM
Odd to have an article on SV, mention VMM and OVM but not mention UVM - perhaps it is merely stale and needs a refresh. — Preceding unsigned comment added by SysTom (talk • contribs) 22:42, 17 January 2014 (UTC)

Use of the programming language infobox
The use of this infobox is strange, since SystemVerilog is not a programming language, despite including much of C++ for writing complex testbenches. As such, the characterization that SystemVerilog is a "structured" programming language for design entry is inaccurate and insufficient in capturing the essence of the language. I've raised the same issue at Talk:Verilog. AZ1199 (talk) 11:33, 3 February 2016 (UTC)