Control register

A control register is a processor register that changes or controls the general behavior of a CPU or other digital device. Common tasks performed by control registers include interrupt control, switching the addressing mode, paging control, and coprocessor control.

History
The early CPU lacked dedicated control registers, and relied on a limited set of internal signals and flags. When IBM developed a paging version of the System/360, they added 16 control registers to the design for what became the 360/67. IBM did not provide control registers on other S/360 models, but made them a standard part of System/370, although with different register and bit assignments. As IBM added new features to the architecture, e.g., DAS, S/370-XA, S/370-ESA, ESA/390, they added additional fields to the control registers. With z/Architecture, IBM doubled the control register size to 64 bits.

Control registers in IBM 360/67
On the 360/67, CR0 and CR2 are used by address translation, CR 4-6 contain miscellaneous flags including interrupt masks and Extended Control Mode, and CR 8-14 contain the switch settings on the 2167 Configuration Unit.

M67 CR0
Control Register 0 contains the address of the segment table for dynamic address translation.

M67 CR2
Control register 2 is the Relocation exception address register.

M67 CR4
CR4 is the extended mask register for channels 0-31. Each bit is the 1/0 channel mask for the corresponding channel.

M67 CR5
CR5 is reserved for the extended mask register for channels 32–63. Each bit is the 1/0 channel mask for the corresponding channel.

M67 CR6
CR6 contains two mode flags plus extensions to the PSW mask bits.

M67 CR8
Control Register 8 contains the assignments of Processor Storage units 1–4 to central processing units (CPUs) and channel controllers (CCs).

M67 CR9
Control Register 9 contains the assignments of Processor Storage units 5–8 to central processing units (CPUs) and channel controllers (CCs).

M67 CR10
Control Register 10 contains the Processor storage address assignment codes.

M67 CR11
Control Register 11 contains channel controller (CC) assignments.

M67 CR12
CR12 contains I/O Control Unit Partitioning.

M67 CR13
CR13 contains I/O Control Unit Partitioning.

M67 CR14
CR14 contains indicators.

Control registers in IBM S/390
The control registers of ESA/390 on the IBM S/390 are an evolutionary enhancement to the control registers on the earlier ESA/370, S/370-XA and S/370 processors. For details on which fields are dependent on specific features, consult the Principles of Operation.

Control registers in IBM z/Architecture
The control registers of z/Architecture are an evolutionary enhancement to the control registers of the earlier ESA/390 on the IBM S/390 processors. For details on which fields are dependent on specific features, consult the Principles of Operation. Because z/Architecture expands the control registers from 32 bits to 64, the bit numbering differs from that in ESA/390.

CR0
The CR0 register is 32 bits long on the 386 and higher processors. On x64 processors in long mode, it (and the other control registers) is 64 bits long. CR0 has various control flags that modify the basic operation of the processor. Register CR0 is the 32 Bit version of the old Machine Status Word (MSW) register. The MSW register was expanded to the Control Register with the appearance of the i386 processor.

CR1
Reserved, the CPU will throw a #UD exception when trying to access it.

CR2
Contains a value called Page Fault Linear Address (PFLA). When a page fault occurs, the address the program attempted to access is stored in the CR2 register.

CR3


Used when virtual addressing is enabled, hence when the PG bit is set in CR0. CR3 enables the processor to translate linear addresses into physical addresses by locating the page directory and page tables for the current task. Typically, the upper 20 bits of CR3 become the page directory base register (PDBR), which stores the physical address of the first page directory. If the PCIDE bit in CR4 is set, the lowest 12 bits are used for the process-context identifier (PCID).

CR4
Used in protected mode to control operations such as virtual-8086 support, enabling I/O breakpoints, page size extension and machine-check exceptions.

CR5–7
Reserved, same case as CR1.

EFER
Extended Feature Enable Register (EFER) is a model-specific register added in the AMD K6 processor, to allow enabling the SYSCALL/SYSRET instruction, and later for entering and exiting long mode. This register becomes architectural in AMD64 and has been adopted by Intel as IA32_EFER. Its MSR number is 0xC0000080.

CR8
CR8 is a new register accessible in 64-bit mode using the REX prefix. CR8 is used to prioritize external interrupts and is referred to as the task-priority register (TPR).

The AMD64 architecture allows software to define up to 15 external interrupt-priority classes. Priority classes are numbered from 1 to 15, with priority-class 1 being the lowest and priority-class 15 the highest. CR8 uses the four low-order bits for specifying a task priority and the remaining 60 bits are reserved and must be written with zeros.

System software can use the TPR register to temporarily block low-priority interrupts from interrupting a high-priority task. This is accomplished by loading TPR with a value corresponding to the highest-priority interrupt that is to be blocked. For example, loading TPR with a value of 9 (1001b) blocks all interrupts with a priority class of 9 or less, while allowing all interrupts with a priority class of 10 or more to be recognized. Loading TPR with 0 enables all external interrupts. Loading TPR with 15 (1111b) disables all external interrupts.

The TPR is cleared to 0 on reset.

XCR0 and XSS
XCR0, or Extended Control Register 0, is a control register which is used to toggle the storing or loading of registers related to specific CPU features using the XSAVE/XRSTOR instructions. It is also used with some features to enable or disable the processor's ability to execute their corresponding instructions. It can be changed using the privileged XSETBV read using the unprivileged XGETBV instructions.

There is also the IA32_XSS MSR, which is located at address. The IA32_XSS MSR controls bits of XCR0 which are considered to be "supervisor" state, and should be invisible to regular programs. It operates with the privileged XSAVES and XRSTORS instructions by adding supervisor state to the data they operate with. Put simply, if the X87 state was enabled in XCR0 and PT state was enabled in IA32_XSS, the XSAVE instruction would only store X87 state, while the privileged XSAVES would store both X87 and PT states. Because it is an MSR, it can be accessed using the RDMSR and WRMSR instructions.