RDRAND

  (for "read random") is an instruction for returning random numbers from an Intel on-chip hardware random number generator which has been seeded by an on-chip entropy source. It is also known as Intel Secure Key Technology, codenamed Bull Mountain. Intel introduced the feature around 2012, and AMD added support for the instruction in June 2015. ( is available in Ivy Bridge processors and is part of the Intel 64 and IA-32 instruction set architectures.)

The random number generator is compliant with security and cryptographic standards such as NIST SP 800-90A, FIPS 140-2, and ANSI X9.82. Intel also requested Cryptography Research Inc. to review the random number generator in 2012, which resulted in the paper Analysis of Intel's Ivy Bridge Digital Random Number Generator.

  is similar to  and provides lower-level access to the entropy-generating hardware. The  generator and processor instruction   are available with Intel Broadwell CPUs and AMD Zen CPUs.

Overview
The  instruction can be used on both AMD and Intel CPUs to check whether the   instruction is supported. If it is, bit 30 of the ECX register is set after calling CPUID standard function. AMD processors are checked for the feature using the same test. availability can be checked on Intel CPUs in a similar manner. If  is supported, the bit 18 of the EBX register is set after calling CPUID standard function.

The opcode for  is , followed by a ModRM byte that specifies the destination register and optionally combined with a REX prefix in 64-bit mode.

Intel Secure Key is Intel's name for both the  instruction and the underlying random number generator (RNG) hardware implementation, which was codenamed "Bull Mountain" during development. Intel calls their RNG a "digital random number generator" or DRNG. The generator takes pairs of 256-bit raw entropy samples generated by the hardware entropy source and applies them to an Advanced Encryption Standard (AES) (in CBC-MAC mode) conditioner which reduces them to a single 256-bit conditioned entropy sample. A deterministic random-bit generator called CTR DRBG defined in NIST SP 800-90A is seeded by the output from the conditioner, providing cryptographically secure random numbers to applications requesting them via the  instruction. The hardware will issue a maximum of 511 128-bit samples before changing the seed value. Using the  operation provides access to the conditioned 256-bit samples from the AES-CBC-MAC.

The  instruction was added to Intel Secure Key for seeding another pseudorandom number generator, available in Broadwell CPUs. The entropy source for the  instruction runs asynchronously on a self-timed circuit and uses thermal noise within the silicon to output a random stream of bits at the rate of 3 GHz, slower than the effective 6.4 Gbit/s obtainable from   (both rates are shared between all cores and threads). The  instruction is intended for seeding a software PRNG of arbitrary width, whereas the   is intended for applications that merely require high-quality random numbers. If cryptographic security is not required, a software PRNG such as Xorshift is usually faster.

Performance
On an Intel Core i7-7700K, 4500 MHz (45 × 100 MHz) processor (Kaby Lake-S microarchitecture), a single  or   instruction takes 110 ns, or 463 clock cycles, regardless of the operand size (16/32/64 bits). This number of clock cycles applies to all processors with Skylake or Kaby Lake microarchitecture. On the Silvermont microarchitecture processors, each of the instructions take around 1472 clock cycles, regardless of the operand size; and on Ivy Bridge processors  takes up to 117 clock cycles.

On an AMD Ryzen CPU, each of the instructions takes around 1200 clock cycles for 16-bit or 32-bit operand, and around 2500 clock cycles for a 64-bit operand.

An astrophysical Monte Carlo simulator examined the time to generate 107 64-bit random numbers using  on a quad-core Intel i7-3740 QM processor. They found that a C implementation of  ran about 2× slower than the default random number generator in C, and about 20× slower than the Mersenne Twister. Although a Python module of  has been constructed, it was found to be 20× slower than the default random number generator in Python, although a performance comparison between a PRNG and CSPRNG cannot be made.

A microcode update released by Intel in June 2020, designed to mitigate the CrossTalk vulnerability (see the security issues section below), negatively impacts the performance of  and   due to additional security controls. On processors with the mitigations applied, each affected instruction incurs additional latency and simultaneous execution of  or   across cores is effectively serialised. Intel introduced a mechanism to relax these security checks, thus reducing the performance impact in most scenarios, but Intel processors do not apply this security relaxation by default.

Compilers
Visual C++ 2015 provides intrinsic wrapper support for the  and   functions. GCC 4.6+ and Clang 3.2+ provide intrinsic functions for  when   is specified in the flags, also setting   to allow conditional compilation. Newer versions additionally provide  to wrap these built-ins into functions compatible with version 12.1+ of Intel's C Compiler. These functions write random data to the location pointed to by their parameter, and return 1 on success.

Applications
It is an option to generate cryptographically secure random numbers using  and   in OpenSSL, to help secure communications.

Scientific application of  in a Monte Carlo simulator was evaluated, focusing on performance and reproducibility, compared to other random number generators. It led to the conclusion that using  as opposed to Mersenne Twister doesn't provide different results, but worse performance and reproducibility.

Reception
In September 2013, in response to a New York Times article revealing the NSA's effort to weaken encryption, Theodore Ts'o publicly posted concerning the use of  for   in the Linux kernel:

"I am so glad I resisted pressure from Intel engineers to let rely only on the   instruction. To quote from the [New York Times article ]: 'By this year, the Sigint Enabling Project had found ways inside some of the encryption chips that scramble information for businesses and governments, either by working with chipmakers to insert back doors...' Relying solely on the hardware random number generator which is using an implementation sealed inside a chip which is impossible to audit is a BAD idea."

Linus Torvalds dismissed concerns about the use of  in the Linux kernel and pointed out that it is not used as the only source of entropy for , but rather used to improve the entropy by combining the values received from   with other sources of randomness. However, Taylor Hornby of Defuse Security demonstrated that the Linux random number generator could become insecure if a backdoor is introduced into the  instruction that specifically targets the code using it. Hornby's proof-of-concept implementation works on an unmodified Linux kernel prior to version 3.13. The issue was mitigated in the Linux kernel in 2013.

Developers changed the FreeBSD kernel away from using  and VIA PadLock directly with the comment "For FreeBSD 10, we are going to backtrack and remove   and Padlock backends and feed them into Yarrow instead of delivering their output directly to /dev/random. It will still be possible to access hardware random number generators, that is, , Padlock etc., directly by inline assembly or by using OpenSSL from userland, if required, but we cannot trust them any more." FreeBSD /dev/random uses Fortuna and RDRAND started from FreeBSD 11.

Security issues
On 9 June 2020, researchers from Vrije Universiteit Amsterdam published a side-channel attack named CrossTalk (CVE-2020-0543) that affected  on a number of Intel processors. They discovered that outputs from the hardware digital random number generator (DRNG) were stored in a staging buffer that was shared across all cores. The vulnerability allowed malicious code running on an affected processor to read  and   instruction results from a victim application running on another core of that same processor, including applications running inside Intel SGX enclaves. The researchers developed a proof-of-concept exploit which extracted a complete ECDSA key from an SGX enclave running on a separate CPU core after only one signature operation. The vulnerability affects scenarios where untrusted code runs alongside trusted code on the same processor, such as in a shared hosting environment.

Intel refers to the CrossTalk vulnerability as Special Register Buffer Data Sampling (SRBDS). In response to the research, Intel released microcode updates to mitigate the issue. The updated microcode ensures that off-core accesses are delayed until sensitive operations – specifically the ,  , and   instructions –  are completed and the staging buffer has been overwritten. The SRBDS attack also affects other instructions, such as those that read MSRs, but Intel did not apply additional security protections to them due to performance concerns and the reduced need for confidentiality of those instructions' results. A wide range of Intel processors released between 2012 and 2019 were affected, including desktop, mobile, and server processors. The mitigations themselves resulted in negative performance impacts when using the affected instructions, particularly when executed in parallel by multi-threaded applications, due to increased latency introduced by the security checks and the effective serialisation of affected instructions across cores. Intel introduced an opt-out option, configurable via the  MSR on each logical processor, which improves performance by disabling the additional security checks for instructions executing outside of an SGX enclave.