VIA PadLock

VIA PadLock is a central processing unit (CPU) instruction set extension to the x86 microprocessor instruction set architecture (ISA) found on processors produced by VIA Technologies and Zhaoxin. Introduced in 2003 with the VIA Centaur CPUs, the additional instructions provide hardware-accelerated random number generation (RNG), Advanced Encryption Standard (AES), SHA-1, SHA256, and Montgomery modular multiplication.

Instructions
The PadLock instruction set can be divided into four subsets:


 * Random number generation (RNG)
 * : Store Available Random Bytes (aka )
 * : Store ECX Random Bytes
 * Advanced cryptography engine (ACE) - for AES crypto; two versions
 * : Electronic code book
 * : Cipher Block Chaining
 * : Counter Mode (ACE2)
 * : Cipher Feedback Mode
 * : Output Feedback Mode
 * SHA hash engine (PHE)
 * : Hash Function SHA-1
 * : Hash Function SHA-256
 * Montgomery multiplier (PMM)

The padlock capability is indicated via a  instruction with. If the resultant, the CPU is aware of Centaur features. An additional request with  then returns PadLock support in. The padlock capability can be toggled on or off with.

VIA PadLock found on some Zhaoxin CPUs have SM3 hashing and SM4 block cipher added.

CPUs with PadLock

 * All VIA Nano CPUs support SHA, AES, and RNG.
 * All VIA Eden CPUs since 2003 (C3 Nehemiah) support AES and RNG. All these released since 2006 support AES, RNG, SHA, and PMM.
 * All VIA C7 CPUs support AES, RNG, SHA, and PMM.

Supporting software

 * Linux kernel since 2.6.11 has PadLock AES. PadLock SHA was introduced in 2.6.19. These are handled as "hardware crypto devices".
 * FreeBSD, NetBSD and OpenBSD support PadLock.
 * OpenSSL supports PadLock AES and SHA since 2004 (0.9.7f/0.9.8a).
 * GNU assembler supports PadLock since 2004.