Talk:Modified Harvard architecture

Confusing
There is no clear explanation on how Modified Harvard architecture is different from Harvard and Von Neumann architectures. Is the architecture of 8086 a Harvard one or Modified Harvard? Secondly, even books on microprocessors or microcontrollers which do explain processor architectures, do not have anything in their books called Modified Harvard architecture. So my question is is there anything called "Modified Harvard Architecture"? Could any expert in this field please clear up this confusion? It would be of great help for me. Thanks, --Abhishek191288 (talk) 17:57, 25 December 2010 (UTC)

The article is vague and non-specific. It confuses two entirely different structures - firstly, a split instruction and data space (as in Harvard) but where data loads can be performed on the instruction space; and secondly, multi-level cache schemes where the inner levels are (pure) Harvard and the outer levels are (pure) von Neumann. —Preceding unsigned comment added by 217.140.96.21 (talk) 15:50, 14 April 2011 (UTC)

I think the issue is that this term was perhaps used at the time, and now everyone is trying to retroactivly apply the principle a lot of this article lacks citation. So at this point the computers where very much different, it may have been a significant thing that essentially you have a computer program (wiring) and a load of data (punchcard) and you perform the same instructions on this data... hence the arbitrary separation. In this sense actually the von neuman architecture, allows the computer and data to be combined, at this time being the superior thing (but slower, the data input speeds being the real bottlenecks). Trying to retroactively apply this, we find in fact all computers are capable of storing instructions and data in memory (in the ram of a program, on the hd). The distinction becomes meaningless all computers are now capable of self modification, we can build a turing complete programming environment quite easily, this means the system is capable of complete self modification (like Von Neumann architecture).DarkShroom (talk) 13:38, 12 October 2013 (UTC)

FWIW: http://ithare.com/modified-harvard-architecture-clarifying-confusion/. In short - it is not Wiki article which is confusing, but is current state of terminology *outside* of Wiki which is confusing; and we as Wikipedians are bound to reflect faithfully this confusing state of terminology :-( . Ipsign (talk) 04:48, 25 September 2015 (UTC)

I think it's great - very helpful
I don't think this article is confusing at all. I didn't check to see if it was improved since the above comments were made, but by my reading of it, it couldn't be more clear -- and was just the information I was looking for. If it's confusing to you, it may be because you don't know what an address space is. If so, I suggest you look at the "Harvard architecture" article as well as the article on "memory space." With that basic understanding, this article couldn't be more clear. I agree it could use some additional cites. --Lenehey (talk) 18:46, 14 August 2011 (UTC)

Microarchitecture vs. instruction-set architecture
This article primarily talks about systems with a single address space for instructions and data, just like "pure" Von Neumann-architecture systems, but with, for example, separate instruction and data caches at levels of the memory hierarchy closest to the processor. Those are, from the point of view of the programmer, far closer to "pure" Von Neumann-architecture systems than to "pure" Harvard-architecture systems; the differences are in the microarchitecture rather than in the instruction set architecture, with the possible exception of, for example, instructions to separately flush instruction and data caches.

It also briefly speaks of systems with two address spaces, one solely for data and one primarily for instructions but with an ability to fetch data from instruction space using separate instructions. Those are, from the point of view of the programmer, closer to Harvard-architecture systems than Von Neumann-architecture systems; they not only differ in the microarchitecture, but also significantly differ in the instruction set architecture.

I.e., the comments by 217.140.96.21 are correct, except that maybe I'd change "It confuses two entirely different structures" to "It conflates two entirely different structures". (And, yes, I understand what an address space is, which is why I know that there are two separate types of architecture here.) Guy Harris (talk) 00:03, 2 September 2011 (UTC)
 * Yes, two different caches is an implementation detail. An x86, ARM, or MIPS that uses a split cache and two buses is just as von Neumann as one that uses a unified cache or no cache. Modified Harvard would be something like the PIC or SHARC varieties that let you read a word from code space into data space. 99.160.56.254 (talk) 18:28, 11 September 2011 (UTC)

split
I suggest splitting this article into 2 articles. As the above comments point out, this article talks about two different ways of modifying the "pure Harvard" architecture. Since each of those ways has been used for large numbers of physical processors, I'm pretty sure each of those ways is notable enough to support its own dedicated Wikipedia article. (Has there been any processors that use *both* of these ways of modifying the "pure Harvard" architecture?) If there is no objection, I suggest moving all the content that discusses CPUs with a separate I-cache and a D-cache into split cache architecture, leaving behind a short note something like "One popular modification of the Harvard architectures is the split cache architecture. The rest of this article focuses on other ways of modifying the Harvard architecture." --DavidCary (talk) 01:55, 20 August 2013 (UTC)


 * If it's rare to refer to a von Neumann architecture with a split cache as a "modified Harvard architecture", then I might not even leave behind the short note - I might just put in a hatnote pointing to the split cache architecture page.


 * Most of the changes involved in a split cache are microarchitecture changes - the main change visible in the instruction set architecture is the possible requirement for an instruction to flush the instruction cache if you store into the instruction stream (and many instruction set architectures, such as x86, have so much code that doesn't expect stores into the instruction stream to require special handling that the microarchitectures of implementations of those instruction sets have to detect those stores and Do The Right Thing, whether it's flushing the instruction cache or the appropriate entry or storing into that entry), so I'd be tempted to just refer to it as "split cache" or refer to it as "split cache microarchitecture and mention I-cache flush instructions in passing. Guy Harris (talk) 05:21, 20 August 2013 (UTC)


 * In my opinion, we should simply say that Harvard / Von Neumann refers to instruction set architecture, and note that the concept of Harvard / Von Neumann architectures predates the concept of microarchitectures and instruction / memory caches. That's how the terms are used in he real world. The core problem is that people trying to explain the concepts somehow think they are obligated to apply it to microarchitecture. --Guy Macon (talk) 07:25, 20 August 2013 (UTC)


 * I.e., don't use the term "Harvard architecture", even modified with "modified", to refer to systems with instructions and data coming from the same memory but with separate I and D caches at some level? Sounds fine to me. Guy Harris (talk) 08:46, 20 August 2013 (UTC)


 * That was my thinking. For example. the page now says..


 * "Most modern computers instead implement a modified Harvard architecture. .. The most common modification builds a memory hierarchy with a CPU cache separating instruction and data."
 * That's wrong. What this describes is a Von Neumann architecture with some caches added. In every Von Neumann computer the data and instructions come from one place and are split before being fed into the ALU. Separate data and instruction caches just split it a bit sooner.
 * In every Harvard computer the data and instructions come from separate places. By focusing on a trivial implementation detail the above passage misses the point entirely. Heck, I could design a Harvard computer that feeds the data and instructions into a single cache before the ALU. That wouldn't make it a Von Neumann computer any more than separate caches turn a Von Neumann computer into a Harvard computer. The key is the source of the data and the instructions, not whether they go though caches, FIFOs or pipelines -- or even get split up and sent to different cores - on the way from memory. --Guy Macon (talk) 11:16, 20 August 2013 (UTC)

Harvard architecture definition
Why some of STM32 family (based on Cortex M3) official claimed to be Harvard arch (not modified Harvard or Von Neuman) if you state at this page what "The true distinction of a Harvard machine is that instruction and data memory occupy different address spaces.". This processor (Cortex M3) has absolutely one adress space for all - code, data, i/o registers and other things. I thing this state wrong and your must get definition from Harvard architecture page — Preceding unsigned comment added by 95.68.195.112 (talk • contribs) 13:23, 4 March 2014‎ (UTC)
 * The terms VN and H are widely used. The term MH is very rarely used, as it has superseded H almost entirely. It is common to use the term H (distinguishing something from VN) to refer to a device that's actually MH. Andy Dingley (talk) 12:58, 4 March 2014 (UTC)
 * I agree with Andy. If you want to be ridiculously pedantic, there is no such thing as a Harvard Architecture that is not a Modified Harvard Architecture. Even the original Harvard Mark I allowed the contents of the instruction memory to be accessed as if it were data. All you had to do was to instruct the operator to read the instructions from the punched paper tape and enter them into the data relays with the Sequence Indicator Switches, then read the results on that Sequence Indicators and punch them into a new tape. Given the 0.33Hz clock rate, this wouldn't even cause a major slowdown. You can do the same with an 8051 using a ROM burner. The definition just says "allows the contents of the instruction memory to be accessed as if it were data". It doesn't strictly say that you can't put a human in the loop.
 * This reminds me of the fact that telegraphs were invented long before electricity became widely available. What we call a "Telegraph" is really and "Electric Telegraph", but the original optical telegraphs became so rare that we didn't need the modifier. Same with "Computer" (which was originally a job title) and "Electronic Computer". --Guy Macon (talk) 14:30, 4 March 2014 (UTC)


 * Who is claiming that some Cortex-M3 processors are Harvard architecture? This page doesn't; the Harvard architecture page does, but I couldn't find anything obvious in the ARMv7-M manual to support that claim, so I asked for a citation on that page.  If you're complaining about the content of Harvard architecture, you should complain on its talk page, not this article's talk page. Guy Harris (talk) 19:55, 4 March 2014 (UTC)

Ok guys, but in this sense i don't like two moments: "...true distinction..." - it's stright way definition of subject (in "Harvard architecture", not in following "Modified Harvard architecture" paragraph) and totaly difference from definition from Harvard architecture page: The Harvard architecture is a computer architecture with physically separate storage and signal pathways for instructions and data. No one words about "different address spaces". If we describe in H,MH and VN in different wiki page we must declare what it's different architectures or stay only 2 - H and VN. I wrong? — Preceding unsigned comment added by 95.68.195.112 (talk • contribs) 18:04, 4 March 2014‎ (UTC)


 * You are certainly right that both pages should be consistent and accurate, and we can do better that we are doing now. The problem is that, if you use the definition "physically separate storage and signal pathways for instructions and data" most modern microprocessors keep program and data in the same RAM chips but have separate caches and pipelines for each. Meanwhile, in the microcontroller world, you often see program in ROM, data in RAM, and a unified cache and pipeline. You might also find a unified L2 cache and separate L1 caches.


 * Now consider one of my favorites, the NXP LPC4000. It has an ARM Cortex M0 (Von Neumann Architecture) and an ARM Cortex M4 (Harvard Architecture) and both processors can access shared memory. --Guy Macon (talk) 18:13, 4 March 2014 (UTC)


 * How is the Cortex-M4 a Harvard architecture processor? I don't see anything obvious in the ARMv7-M architecture manual that indicates that code and data exist in separate address spaces, such that a load or store can't access code; in fact, the Instruction Synchronization Barrier (ISB) section of the manual speaks of modifying instructions in memory.  (The manual refers to a "Harvard architecture of caches", but that's just talking about split I&D caches.) Guy Harris (talk) 19:42, 4 March 2014 (UTC)


 * And, no, I don't consider a processor with some or all code running from ROM to be a Harvard-architecture processor, I consider it a von Neumann-architecture processor where stores into some regions of the address space are no-ops or cause faults. I view the inability to use regular data load instructions to fetch the contents of the code memory and to use regular data store instructions to modify the contents of the code memory as a sine qua non of a Harvard architecture; a pure Harvard architecture would lack even specialized instructions to load from or store into code memory, a modified Harvard architecture might have one or both of those. Guy Harris (talk) 19:52, 4 March 2014 (UTC)

Ok, I understand your position and, i think, you understand my. What are you think about enterly two different terms for this reason - "historical" and "current assumptions" ("current practical using")? — Preceding unsigned comment added by 95.68.195.112 (talk • contribs) 19:23, 4 March 2014‎ (UTC)


 * That's a really good idea. --Guy Macon (talk) 19:28, 4 March 2014 (UTC)

Many question about who claimed what "Cortex-M3 is Harvard" - official ARM and STM documents - example, Cortex™-M3 Technical Reference Manual (ARM DDI 0337E) citation: The processor core implements the ARMv7-M architecture. It has the following main features: • Thumb-2 (ISA) subset consisting of all base Thumb-2 instructions, 16-bit and 32-bit. • Harvard processor architecture enabling simultaneous instruction fetch with data load/store. — Preceding unsigned comment added by 95.68.232.18 (talk • contribs) 05:19, 5 March 2014‎ (UTC)


 * OK, that's by the definition of "Harvard architecture" that says it means "separate I&D caches". If I had a time machine, and could go back in time and convince whoever the first person to call that a "Harvard architecture" not to do so, I would do so in a heartbeat - it basically renders the term "Harvard architecture" not particularly interesting.  What do a machine where the code and data come from the same address space, where the processor can write code to memory and later execute it, and where there are separate level-1 caches for code and data, and a machine where the code and data come from separate address spaces, with memory attached by separate buses or with all memory being on-chip with separate signal lines, and no caches, have in common?


 * So, sadly, people out there in the real world use "Harvard architecture" to mean whatever they want it to mean, and there's not much Wikipedia can do about it. This page reflects that; see the "Split cache architecture", "Access instruction memory as data", and "Read instructions from data memory" subsections of the "Modified Harvard architecture" section.  The Cortex-M3 - and the Core i7 on the machine on which I'm typing this! - are "modified Harvard architecture" processors in the "split cache architecture" sense; they fetch code and data from the same address space, they support storing into the instruction stream and, for backward-compatibility reasons, the Core i7 (and every x86 process that's ever had a cache) supports that transparently (at least according to the ARMv7-M manual, storing into the instruction stream requires some care to make sure that the pipeline doesn't process an out-of-date version of a modified instruction).  Some DSPs and microcontrollers are either pure Harvard architecture processors (with no data access to the code at all from the processor) or modified Harvard architecture processors in the "access instruction memory as data" sense. Guy Harris (talk) 04:42, 5 March 2014 (UTC)


 * I think we have only one "time machine" - two distinct definition of the some term - "historical" and "current use" or you think that ARM technical writers wrong? — Preceding unsigned comment added by 95.68.232.18 (talk • contribs) 04:59, 5 March 2014‎ (UTC)


 * Historically, machines were simple enough that separate data paths between the processor and the memories, and separate address spaces, were the same thing. In current use, sometimes "Harvard architecture" means "the CPU fetches instructions from the I-cache and data from the D-cache, but fills both of them from the same memory", and sometimes it means "there really are separate address spaces for code and data", so there is no "current use" definition, there are (at least) two "current use" definitions, plural, one of which is the same as the "historical" definition.


 * And I think the first of the two "current use" definitions is not a good definition. As far as I'm concerned, split I&D caches are 99 44/100% a technical trick to allow a von Neumann-architecture machine to get rid of most of the competition for the memory bus between code and data accesses, not a Fundamental Architecture Difference; the only way in which it's an Architecture Difference is that, in some such processors (ones for which the backwards-compatibility requirements weren't too large), you might have to flush the I-cache, or a particular I-cache line, when storing into the instruction stream.  Separate address spaces, however, is a big architecture difference; it means you either can't do on-the-fly code generation, and can't load new code to be executed, or you need special instructions to do that.  Those might not be big issues in the microcontroller or DSP world, which is why some microcontrollers and DSPs have pure Harvard or Harvard-with-instruction-stream-load architectures, but it's a big issue for general-purpose computing (which includes smartphones and tablets), so that's why few, if any, other processors have real Harvard architectures, as opposed to "von Neumann with split I&D L1 caches" architectures.


 * And, frankly, I'd prefer it if people stopped using "Harvard architecture" to mean "von Neumann with split I&D L1 cache architecture", and "people" includes ARM here. Guy Harris (talk) 06:17, 5 March 2014 (UTC)


 * By the way, the Cortex-M3 Revision r2p1 Technical Reference Manual does not say anything about a "Harvard processor architecture enabling simultaneous instruction fetch with data". What it does indicate is that instruction fetches from the address region 0x00000000-0x1FFFFFFF go over one bus, data accesses to that region go over another bus, and all references to the regions 0x20000000-0xDFFFFFFF and 0xE0100000-0xFFFFFFFF go over a third bus.  That's not what I'd consider a "Harvard architecture" in the "instruction set architecture" sense, and it's not even "Harvard architecture" in the "hardware architecture" sense, as far as I'm concerned, given that there are two buses for the same region of memory, one used for instruction fetches and one used for data accesses - and a third bus used for both instruction fetches and data accesses to another couple of regions. Guy Harris (talk) 06:35, 5 March 2014 (UTC)


 * Ok, and now we can delete Cortex-M3 words in "They also mean that instruction prefetch can be performed in parallel with other activities. Examples include, the AVR by Atmel Corp, the PIC by Microchip Technology, Inc. and the ARM Cortex-M3 processor[citation needed] (not all ARM chips feature a Harvard architecture)." sentence at Harvard architecture, because ARM infocenter delete this claim? (I recognize AVR and PIC arch like Harvard, but, from my POV, i can't do this for ARM Cortex-M3) — Preceding unsigned comment added by 95.68.232.18 (talk • contribs) 08:18, 5 March 2014‎ (UTC)


 * I added the "citation needed" tag for the bit about the Cortex-M3; I'll remove the claim that it has a Harvard architecture. Guy Harris (talk) 08:47, 5 March 2014 (UTC)

ARM Cortex M3: Harvard, Modified Harvard, or Von Neuman?
Note: I haven't used the m3 specifically (I usually use an M0 or M4F), so this is from the literature, not personal experience.


 * "The central Cortex-M3 core is based on the Harvard architecture characterized by separate buses for instructions and data (Figure 3). The processor differs from the Von Neumann architecture based ARM7 family of processors which use the same signal buses and memory for both instructions and data. By being able to read both an instruction and data from memory at the same time, the Cortex-M3 processor can perform many operations in parallel, speeding application execution."


 * "The Cortex-M3 is a 32-bit microprocessor. It has a 32-bit data path, a 32-bit register bank, and 32-bit memory interfaces. The processor has a Harvard architecture, which means it has a separate instruction bus and data bus. This allows instructions and data access to take place at the same time..."[books.google.com/books?id=T9heqSaErCcC&pg=PA13&lpg=PA13&dq=harvard]


 * "The ARM Cortex-M3 is an implementation of the ARM7v architecture, the latest evolution of ARM’s embedded cores. It is a Harvard architecture, using separate buses for instructions and data (rather than a Von Neumann architecture, where data and instructions share a bus)."


 * "Cortex-M3 also has separate buses for instructions and data. The Harvard architecture reduces bottlenecks common to shared data- and instruction buses."


 * "Key features of Cortex-M3 Core ... It’s a Harvard architecture(separate instruction bus and data bus):


 * "What is the use of Harvard architecture?? This architecture allows instructions and data access to take place at the same time. Therefor in Cortex-M3, multiple bus interfaces, each with optimized usage and the ability to be used simultaneously. But don’t expect that we have two separate 32-bit buses so we can have 4GB + 4GB = 8GB of memory space. These two buses share the same memory space."


 * "Cortex-M3 architecture: Harvard architecture: separate instruction and data buses"

Here is an important detail: Look at the block diagram at that last cite, then read the penultimate cite again. Two separate data paths. Two separate memories. One unified address space.

Ah, but what about writing to program memory? At this page the author tested the following:


 * 1) Trying to read at an address that is reserved in the memory map (i.e. no physical memory there)
 * 2) Trying to write to Flash/ROM
 * 3) Stopping areas of memory being accessible
 * 4) Disable running code located in SRAM

To test these. he set up the following tests:


 * 1) Read from location 0×0008 0000 – this is beyond Flash in a reserved area of memory
 * 2) Write to location 0×0000 4000 – some random location in the flash region
 * 3) Read the boot ROM at 0x1FFF 0000
 * 4) Construct a function in SRAM and execute it

Without the Memory Protection Unit (MPU) configured, here were the results:


 * 1) Generates a precise bus error
 * 2) Generates an imprecise bus error
 * 3) Runs without any fault being generated.
 * 4) Runs without any fault being generated.

After configuring the Memory Protection Unit (MPU), here were the results:


 * 1) Memory Management Fault: Data access violation
 * 2) Memory Management Fault: Data access violation
 * 3) Memory Management Fault: Data access violation
 * 4) Memory Management Fault: MPU or Execute Never (XN) default memory map access

--Guy Macon (talk) 13:41, 5 March 2014 (UTC)


 * And then there's


 * System interface


 * Instruction fetches, and data and debug accesses, to address ranges 0x20000000 to 0xDFFFFFFF and 0xE0100000 to 0xFFFFFFFF are performed over this 32-bit AHB-Lite bus.
 * For simultaneous accesses to this bus, the arbitration order in decreasing priority is:
 * data accesses
 * instruction and vector fetches
 * debug.
 * The system bus interface contains control logic to handle unaligned accesses, FPB remapped accesses, bit-band accesses, and pipelined instruction fetches.


 * on page 2-5 of the Cortex-M3 Revision r2p1 Technical Reference Manual, which sounds more von Neumann-like than Harvard-like. Perhaps it's time we add a third category, "hybrid Harvard/von Neumann architecture", or something such as that. Guy Harris (talk) 17:44, 5 March 2014 (UTC)

Von Neumann
First let me say I am sorry to bother you as I am everything except an expert in this field. However in the the Von Neumann section it is said that it has to advantage over pure Havard because two steps can be done at the same time. I guess it should be the other way around as Von Neumann shares just one memory space and one bus so it can either read/write data from/to the memory. In comparision Harvard has two memory spaces with two busses. But I can be mistaken. — Preceding unsigned comment added by 192.162.151.245 (talk) 15:20, 21 May 2015 (UTC)


 * No, it is not said that the von Neumann architecture's advantage over the Harvard architecture is that "two steps can be done at the same time". What is said is


 * A computer with a Von Neumann architecture has the advantage over pure Harvard machines in that code can also be accessed and treated the same as data, and vice versa.


 * There's no "at the same time" there.


 * What that means is that, in a pure Harvard architecture machine, a program cannot write out a section of data to memory and then, after it does that, execute that data as machine code, but, in a von Neumann architecture machine, a program can do so. That is, in fact, correct.  The article says


 * This allows, for example, data to be read from disk storage into memory and then executed as code, or self-optimizing software systems using technologies such as just-in-time compilation to write machine code into their own memory and then later execute it.


 * which indicates that putting the code into memory and executing it are separate steps, with the first step performed before the second step. (I just edited that to add "then" before "executed as code" to make that clearer.) Guy Harris (talk) 17:56, 21 May 2015 (UTC)